CPU Pin Assignments


386SX
386DX (PGA)
486SX ~ DX4
486DX4 ~ 5x86


386SX Pin Assignment

Pin Signal Pin Signal Pin Signal Pin Signal
1 D0 26 LOCK# 51 A2 76 A21
2 Vss 27 NC 52 A3 77 Vss
3 HLDA 28 FLT# 53 A4 78 Vss
4 HOLD 29 NC 54 A5 79 A22
5 Vss 30 NC 55 A6 80 A23
6 NA# 31 NC 56 A7 81 D15
7 READY# 32 Vcc 57 Vcc 82 D14
8 Vcc 33 RESET 58 A8 83 D13
9 Vcc 34 BUSY# 59 A9 84 Vcc
10 Vcc 35 Vss 60 A10 85 Vss
11 Vss 36 ERROR# 61 A11 86 D12
12 Vss 37 PEREQ 62 A12 87 D11
13 Vss 38 NMI 63 Vss 88 D10
14 Vss 39 Vcc 64 A13 89 D9
15 CLK2 40 INTR 65 A14 90 D8
16 ADS# 41 Vss 66 A15 91 Vcc
17 BLE# 42 Vcc 67 Vss 92 D7
18 A1 43 NC 68 Vss 93 D6
19 BHE# 44 NC 69 Vcc 94 D5
20 NC 45 NC 70 A16 95 D4
21 Vcc 46 NC 71 Vcc 96 D3
22 Vss 47 NC 72 A17 97 Vcc
23 M/IO# 48 Vcc 73 A18 98 Vss
24 D/C# 49 Vss 74 A19 99 D2
25 W/R# 50 Vss 75 A20 100 D1


386DX (PGA) Pin Assignment

Pin Signal Pin Signal Pn Signal Pin Signal Pin Signal Pin Signal
A1 Vcc B9 BUSY# D3 A9 H1 A17 L13 D8 N7 Vcc
A2 Vss B10 W/R# D12 Vcc H2 A18 L14 D6 N8 D23
A3 A3 B11 Vss D13 NA# H3 A19 M1 A26 N9 D21
A4 NC B12 NC D14 HOLD H12 D0 M2 A29 N10 D17
A5 Vcc B13 BE2# E1 A14 H13 D1 M3 Vcc N11 D16
A6 Vss B14 Vss E2 A13 H14 D2 M4 Vss N12 D12
A7 Vcc C1 A8 E3 A12 J1 A20 M5 D31 N13 D11
A8 ERROR# C2 A7 E12 BE0# J2 Vss M6 D28 N14 D9
A9 Vss C3 A6 E13 NC J3 Vss M7 Vcc P1 A30
A10 Vcc C4 A2 E14 ADS# J12 Vss M8 Vss P2 Vcc
A11 D/C# C5 Vcc F1 A15 J13 Vss M9 D20 P3 D30
A12 MI/O# C6 NC F2 Vss J14 D3 M10 Vss P4 D29
A13 BE3# C7 NC F3 Vss K1 A21 M11 D15 P5 D26
A14 Vcc C8 PEREQ F12 CLK2 K2 A22 M12 D10 P6 Vss
B1 Vss C9 RESET F13 NC K3 A25 M13 Vcc P7 D24
B2 A5 C10 LOCK# F14 Vss K12 D7 M14 HLDA P8 Vcc
B3 A4 C11 Vss G1 A16 K13 D5 N1 A27 P9 D22
B4 NC C12 Vcc G2 Vcc K14 D4 N2 A31 P10 D19
B5 Vss C13 BE1# G3 Vcc L1 A23 N3 Vss P11 D18
B6 NC C14 BS16# G12 Vcc L2 A24 N4 Vcc P12 D14
B7 INTR D1 A11 G13 READY# L3 A28 N5 D27 P13 D13
B8 NMI D2 A10 G14 Vcc L12 Vcc N6 D25 P14 Vss


486 Pin Assignment

SX DX/DX2 ODP AM DX2 *1 i486DX4 DX4ODP AMD DX4 CxDX2
A3 NC TCK NC TCK TCK NC TCK NC
A10 NC NC NC NC ** NC NC SUSPA#
A12 NC NC NC NC NC NC SMI#
A13 NC NC FERR# NC NC FERR# NC RPLSET1
A14 NC TDI NC TDI TDI NC TDI NC
A15 NMI IGNNE# IGNNE# IGNNE# IGNNE#
B10 NC NC NC SMI# SMI# NC NC
B13 NC NC CLKMUL *2 NC NC CLKMUL *2
B14 NC TMS UP# Out TMS TMS UP# Out TMS
B15 NC NMI NMI NMI NMI
B16 NC TDO NC TDO TDO NC TDO
C3 CLM CLK CLK CLK CLK
C10 NC NC NC SRESET NC NC SMADS
C11 NC UP# In NC UP# NC
C12 NC NC NC SMIACT# SMIACT# NC RPLSET0
C13 NC NC NC NC NC NC RPLVAL#
C14 NC FERR# NC FERR# NC
G15 NC NC NC NC STPCLK# STPCLK# NC SUSP#
J1 VCC VCC VCC5 VCC5 NC NC
R17 NC NC NC CLKMUL*2 CLKMUL *2 NC
S4 NC NC NC VOLDET VOLDET VOLDET VOLDET INVAL
D4 --- --- KEY --- --- KEY --- ---
SX SX ODP AM DX2 *1 i486DX4 DX4ODP AMD DX4 CxDX2

*1 AMD DX2 3.3V PART
*2 to Vss: 2x, NC=Open (Internally Pull-Up): 3x
(AMD DX2 5V part does not have CLKMUL pin)


486 Pin Assignment (2)

i486DX4 DX4ODP AM DX4 AM 5x86 CxDX2 CxDX4 ST5x86
A3 TCK NC TCK TCK NC TCK
A10 NC ** NC NC INV SUSPA# INVAL
A12 NC NC NC HITM SMI# HITM#
A13 NC FERR# NC NC RPLSET1 SUSPA#
A14 TDI NC TDI TDI NC TDI
A15 IGNNE# IGNNE# IGNNE# IGNNE#
B10 SMI# SMI# NC SMI# NC SMI#
B13 NC NC CLKMUL *2 WB/WT NC
B14 TMS UP# Out TMS TMS TMS
B15 NMI NMI NMI NMI
B16 TDO NC TDO TDO TDO
C3 CLK CLK CLK CLK
C10 SRESET NC NC SRESET SMADS WM_RSET
C11 UP# NC UP# UP#
C12 SMIACT# SMIACT# NC SMIACT RPLSET0 SMADS
C13 NC NC NC NC RPLVAL# NC
C14 FERR# NC FERR# FERR#
G15 STPCLK# STPCLK# NC STPCLK# SUSP# SUSP#
J1 VCC5 VCC5 NC NC NC NC
R17 CLKMUL*2 CLKMUL *2 NC CLKMULT *3 CLKMULT
S4 VOLDET VOLDET VOLDET VOLDET INVAL VOLDET
D4 --- KEY --- ---- ---
i486DX4 DX4ODP AM DX4 AM 5x86 CxDX2 CxDX4 ST5x86

*1 AMD DX2 3.3V PART
*2 to Vss: 2x, NC=Open (Internally Pull-Up): 3x
*3 to Vss: 4x, NC=Open (Internally Pull-Up): 3x

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Louis F. Ohland, Peter H. Wendt, David L. Beem, William R. Walsh, Tatsuo Sunagawa, Tomáš Slavotínek, Jim Shorney, Tim N. Clarke, Kevin Bowling, and many others.

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