Serial Diagnostic Link for PS/2 Model 95 Processor Cards Disclosed is a Serial Diagnostic Link (SDL) for the PS/2* Model 90 and 95 information panel, allowing the main system processor direct access to the alphanumeric display. This display is used during Power-On Self-Test and during error conditions, as information regarding the execution of the processor is reported to the user. With the SDL, the main processor does not have to rely on the operational condition of any other system function to display information on the alphanumeric display. Without the SDL, the Model 95 information panel interface can be used by the main processor only when the Micro Channel*, the planar board VLSI, and the processor complex card interface are the functional. The SDL is a three-signal interface. Output signals from the processor card, which are input signals to the information panel used to program the alphanumeric display, are DISPLAY_STROBE, and DISPLAY_RESET. The DISPLAY_SENSE signal is an input to the processor card from the information panel, which is the logical NOT of the DISPLAY_STROBE. The DISPLAY_SENSE signal is used by the processor to determine the presence of the SDL and to provide a real-time mechanism for monitoring the SDL itself. The interface is operated in a uni-directional mode, with all information emanating from the processor card. The support hardware on the processor card and on the information panel for this function is minimal. On the processor card, this logic provides two bits in an I/O WRITE port, corresponding to the DISPLAY_STROBE and DISPLAY_RESET signals, and one bit in an I/O READ port, corresponding to the DISPLAY_SENSE signal. The operation of these signals by the processor is done entirely with software. On the display panel, logic transforms the incoming SDL bit stream into the existing parallel interrace to remain compatible with the alphanumeric display. The duration of signal levels for this interface are defined only by minimums. Since these minimums are less than the times available in processor card bus cycles, in effect these signals are timing-independent. No clocking mechanisms are required for this interface. While the timing of the signals is thus independent, the sequence of their operation is not. As shown in Fig. 2, five stages must be performed in the following order---initial, count/latch, validate/reset, write character, and validate/hold. The initial stage is entered on a high-to-low transition of the DISPLAY_RESET signal. The state of DISPLAY_STROBE is a "don't care" condition when entering this stage. Upon entering this stage, all logic on the information panel and processor card is reset, awaiting the transmission of the output character information. The count/latch stage is entered when the processor produces a high-to-low transition of the DISPLAY_STROBE signal. In this stage, every high-to-low transition is considered a "count," and every low-to-high transition is considered a "latch." The logic on the information panel sequences the "counts" through a 74F393 ripple counter, the outputs of which are defined as the parallel interface signals necessary to operate the alphanumeric display. In this way, a simple serial to parallel interface conversion is performed by the ripple counter. The "latch" is used to latch the previous parallel output of the ripple counter into a 74F373 register, so that the ripple counter may be reset in the next stage without destroying the "count" data. The write character stage is entered on a high-to-low transition of DISPLAY_STROBE while DISPLAY_RESET is high. Upon entering this stage, the data is written to the display, and a character appears at the correct address location. The validate/hold stage is entered on the low-to-high transition of the DISPLAY_STROBE signal while DISPLAY_RESET is high. Upon entering this stage, the data is written to the display, and a character appears at the correct address location. The initial stage is re-entered from the validate/hold stage by the high-to-low transition of the DISPLAY_RESET signal. At this point, the SDL and information panel are ready for the next output character. Programming, by the system code, for the stages described above is straightforward. The following pseudo code shows the general flow of the stages, with character data values necessary to display ASCII characters at each address location of the alphanumeric display: OUT DISPLAY_STROBE,1 ; Power on reset OUT DISPLAY_RESET,1 ; These three statements are done at first power OUT DISPLAY_RESET,0 ; on to get into the initial stage TOP: Move CX, Character ; place the data to be displayed in a Begin: ; decrement register. Enter Count/Latch ; stage first time thru loop. OUT DISPLAY_STROBE,0 ; Provide a "count" OUT DISPLAY_STROBE,1 ; Provide a "latch" LOOP Begin ; Decrement the data, loop until done. OUT DISPLAY_RESET,1 ; Enter validate/reset stage OUT DISPLAY_STROBE,0 ; Enter write character stage OUT DISPLAY_STROBE,1 ; Enter validate/hold stage OUT DISPLAY_RESET,O ; Enter initial stage ; Go to TOP to output the next character.