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ACPA Expansion Bus Pinout

Pin	Signal	Definition	Dir	Pin	Signal	Definition	Dir
1	CLKIN	Input INT OSC [40MHz]	I	31	+12 Vdc	??? (via 10 Ω R)
2	-RS	Reset input	I	32	READY	Data ready input	I
3	N/C			33	-INT2/0	External user interrupt input	I
4	Vss	Ground	I	34	Vss	Ground	I
5	Vcc	+5V dc	I	35	-HOLD	Hold input [idle mode]	I
6	CLKX	CLK serial port xmit output	I	36	CLKR	CLK for serial port recv input	I
7	D15	Data bus D15 [M] [MSB]	I/O/Z	37	D14	Data bus D14 [M]	I/O/Z
8	D13	Data bus D13 [M]	I/O/Z	38	D12	Data bus D12 [M]	I/O/Z
9	D11	Data bus D11 [M]	I/O/Z	39	D10	Data bus D10 [M]	I/O/Z
10	D9	Data bus D9 [M]	I/O/Z	40	D8	Data bus D8 [M]	I/O/Z
11	D7	Data bus D7 [M]	I/O/Z	41	D6	Data bus D6 [M]	I/O/Z
12	D5	Data bus D5 [M]	I/O/Z	42	D4	Data bus D4 [M]	I/O/Z
13	D3	Data bus D3 [M]	I/O/Z	43	D2	Data bus D2 [M]	I/O/Z
14	D1	Data bus D1 [M]	I/O/Z	44	D0	Data bus D0 [M] [LSB]	I/O/Z
15	DR	Serial data receive input	I	45	DX	Serial data transmit output	O/Z
16	Vss	Ground	I	46	-HOLDA	Hold acknowledge signal	O
17	Vcc	+5 Vdc	I	47	Vss	Ground	I
18	-STRB	Strobe signal	O/Z	48	FSX	Frame synch pulse for xmit.	I/O/Z
19	-PS	Program select signal	O/Z	49	R/-W	Read/write signal	O/Z
20	-IS	I/O space select signal	O/Z	50	FSR	Frame synch pulse for recv input	I
21	A0	Address bus A0 [LSB]	O/Z	51	-DS	Data select signal	O/Z
22	A2	Address bus A2	O/Z	52	A1	Address bus A1	O/Z
23	A4	Address bus A4	O/Z	53	A3	Address bus A3	O/Z
24	A6	Address bus A6	O/Z	54	A5	Address bus A5	O/Z
25	A8	Address bus A8	O/Z	55	A7	Address bus A7	O/Z
26	A10	Address bus A10	O/Z	56	A9	Address bus A9	O/Z
27	A12	Address bus A12	O/Z	57	A11	Address bus A11	O/Z
28	A14	Address bus A14	O/Z	58	A13	Address bus A13	O/Z
29	Vcc	+5 Vdc	I	59	A15	Address bus A15 [MSB]	O/Z
30	Vss	Ground	I	60	Vss	Ground	I

Notes:
All Data Bus and Address Bus lines are 16-bit.
All Data Bus Lines are Multiplexed between program, data, and I/O spaces
PS, DS, IS select the Program, data, and I/O space used by Data Bus and Address Bus
I/O/Z denotes input/output/high-impedance state.

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