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Real-Time Clock Bytes (Hex 000-00D)
Status Register A (Hex 00A)
Status Register B (Hex 00B)
Status Register C (Hex 00C)
Status Register D (Hex 00D)
Real-Time Clock Bytes (Hex 000-00D)
Bit definitions and addresses for the Real-Time Clock
bytes are shown in the following figure.
00 Seconds
01 Second alarm
02 Minutes
03 Minute alarm
04 Hours
05 Hour alarm
06 Day of week
07 Date of month
08 Month
09 Year
0A Status Register A
0B Status Register B
0C Status Register C
0D Status Register D
Note: The Setup program initializes
Status Register A and Status Register B when the time and date are set.
Interrupt 1Ah is the BIOS interface that is used to read and set the time
and date; it initializes the registers in the same way that the Setup program
does.
Status Register A (Hex 00A)
+--------------------------------------------------------+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|------+--------------+-------+--------------------------|
| UIP | SDIV | BC | Rate |
+--------------------------------------------------------+
UIP: Update in progress
SDIV: Select divider
BC: Bank control
RATE: Rate select
UIP The update-in-progress
bit is a read-only bit that indicates when the time and date registers
are being updated. When the bit is 1, an update is in progress. When it
is set to 0, the current date and time can be read.
SDIV This two-bit field specifies
the time-base frequency is being used. The system initializes these bits
to binary 01, which selects a 32.768-kHz time base. This is the only value
that is supported by the system for proper timekeeping.
BC The bank-control bit selects
the bank of CMOS RAM that is accessed through the real-time clock.
When this bit is set to 0, bank 0 is accessed through the RTC Data register.
When this bit is set to 1, bank 1 is accessed.
Rate This four-bit field selects
the divider output frequency. The system initializes these bits to a binary
0110, which selects a 1.024-kHz square-wave output frequency and a 976.562-microsecond
periodic interrupt rate.
Status Register B (Hex 00B)
+-----------------------------------------------+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|-----+-----+-----+-----+-----+-----+-----+-----|
| SET | PIE | AIE | UIE | SQW | DM |24/12| DSE |
+-----------------------------------------------+
SET: Set clock
PIE: Enable periodic int
AIE: Enable alarm int
UIE: Enable update-ended int
SQW: Enable square-wave
DM: Date mode
24/12: 24-Hour mode
DSE: Enable daylight saving
SET When this bit is set to
0, the clock updates the cycle normally by advancing the count at a rate
of one per second. When this bit is set to 1, the clock immediately ends
any update cycle in progress, and the program can initialize the 14 time
bytes without updates occurring until this bit is reset to 0.
PIE The period-interrupt-enable
bit enables an interrupt to occur at a rate that is specified by the rate
and divider bits in Status Register A. When this bit is set to 1, the interrupt
is enabled. The system initializes this bit to 0.
AIE The alarm-interrupt-enable
bit enables an interrupt to occur when the time matches the values specified
in the alarm bytes. When this bit is set to 1, the alarm interrupt is enabled.
The system initializes this bit to 0.
UIE The update-interrupt-enable
bit enables an interrupt t occur when the clock has completed an update
cycle. When this bit is set to 1, the update-ended interrupt is enabled.
The system initializes this bit to 0.
SQW The square-wave-enable
bit determines whether the square-wave generator is enabled. When this
bit is set to 1, the generator is enabled and uses the frequency specified
by the rate-selection bits in Status Register A. The system initializes
this bit to 0.
DM The date-mode bit specifies
whether the internal counters use binary-coded-decimal (BCD) or binary
format for time-and-date calendar updates. When this bit is set to 1, the
binary format is used. The system initializes this bit to 0.
24/12 The 24/12-hour bit specifies
whether the hour byte is in 12-hour or 24-hour mode. When this bit is set
to 1, the 24-hour mode is used. The system initializes this bit to 1.
DSE When this bit is set to 1, the
daylight-saving-time mode is enabled. When this bit is set to 0, the
daylight-saving-time mode is disabled, and the clock reverts to standard time.
The system initializes this bit to 0.
Status Register C (Hex 00C)
+-----------------------------------------------+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|-----+-----+-----+-----+-----------------------|
| IRQ | PF | AF | UF | Reserved |
+-----------------------------------------------+
IRQ: Interrupt-request
PF: Periodic-interrupt
AF: Alarm-interrupt
UF: Update-ended interrupt
Note: Interrupts are enabled by
bits 6, 5, and 4 in Status Register B and Extended Control Register A.
IRQ The interrupt-pending
bit indicates that the real-time clock has a system interrupt pending.
When this bit is 1, the real-time clock has generated a system interrupt.
Bits 6, 5, and 4 in this register and bits 2 through 0 in Extended Control
Register A indicate the cause of the interrupt.
Note: The interrupt-pending
bit is normally reset when this register is read; however, for interrupts
in Extended Control Register A, the interrupt must first be cleared by
resetting the corresponding bit to 0 (see Extended Control Register
A (Hex 4A)).
PF When this bit is 1, a periodic
interrupt occurred.
AF When this bit is 1, an alarm interrupt
occurred.
UF When this bit is 1, an update-ended
interrupt occurred.
Status Register D (Hex 00D)
+-----------------------------------------------+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|-----+-----------------------------------------|
| VM | Reserved |
+-----------------------------------------------+
VM: Valid RAM
VM The valid-RAM
bit is a read-only bit that indicates whether the contents of CMOS RAM
is good. When this bit is 1, the data of CMOS RAM is considered valid;
when the bit is 0, the data in CMOS is no longer valid.
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