Brighton Component Specification

Version 2.00.1

September, 1996

Table of Contents

  • 0.1 Some Conventions
  • 0.2 Brighton Overview
  • 0.2.1 General Description
  • 0.2.2 Features
  • 0.2.3 Performance
  • 0.2.4 Block Diagrams
  • 0.2.5 Data/Address Paths

    • 1.0 Brighton Signal Description

  • 1.1 80960CA Interface
  • 1.2 Local Bus Interface
  • 1.3 DRAM Interface
  • 1.4 Other Interface Signals

    • 2.0 Brighton Addressable Registers

  • 2.1 Timer Control Register (TCR0-4)
  • 2.2 Timer Preset Register (TPR0-4)
  • 2.3 Timer Present Value register (TPV0-4)
  • 2.4 Timer Command Register (TCMD0-4)
  • 2.5 Transmitter Buffer Port (TxBUF)
  • 2.6 Receiver Buffer Port (RxBUF)
  • 2.7 Port Configuration Register (PCR)
  • 2.8 Memory Protection Enable Register (MPER)
  • 2.9 Task Page Table Base Register (TASK_PTBR)
  • 2.10 Master0 Page Table Base Register (MC_PTBR)
  • 2.11 Master1 Page Table Base Register (AM_PTBR)
  • 2.12 Task Protection Address Trap Register (TPATR)
  • 2.13 Task Protection Status Register (TPSTAT)
  • 2.14 Local Bus Protection Address Trap Register (LPATR)
  • 2.15 Local Bus Protection Status Register (LPSTAT)
  • 2.16 Local Bus Exception Address Trap Register (LEXATR)
  • 2.17 Local Bus Exception Status Register (LEXSTAT)
  • 2.18 Single-bit ECC Error Address Trap Register (SBATR)
  • 2.19 Single-Bit ECC Error Register (SBECCR)
  • 2.20 ECC Address Trap Register (ECCATR)
  • 2.21 ECC Status Register (ECCSTAT)
  • 2.22 Gate Array ID Register (GAIDR)
  • 2.23 Memory Configuration Register (MCR)
  • 2.24 Special Arbitration Register (SPAR)
  • 2.25 Local Bus Configuration Register (LBCFG)
  • 2.26 Force ECC Error Register (FEER)

    • 3.0 Memory Controller(s)

  • 3.1 Memory Organization and Addressing
  • 3.2 Memory Size
  • 3.3 Memory Speed
  • 3.4 Memory Map
  • 3.4.1 80960 Memory Map
  • 3.4.2 Local Bus Memory Map
  • 3.5 Error Correction Code (ECC)
  • 3.5.1 ECC Errors

    • 4.0 Local Bus Accesses by Brighton

    5.0 Arbiter Function

  • 5.1 Packet Memory Arbiter
  • 5.2 Instruction Memory Arbiter
  • 5.3 Local Bus Arbiter
  • 5.3.1 Preemption
  • 5.4 Special Arbitration Modes
  • 5.5 Local Bus Timeout

    • 6.0 Memory Protection

  • 6.1 Page Table Entries
  • 6.2 Page Tables
  • 6.3 Page Table Entry Caching
  • 6.4 How It Works
  • 6.5 Usage Notes for Memory Protection

    • 7.0 Brighton Timers

  • 7.1 Timer Interrupts

    • 8.0 Brighton Serial Debug Port

  • 8.1 Serial Debug Port Interrupts

    • 9.0 Interrupt Function

  • 9.1 Manufacturing Test
  • 9.1.1 Driver Inhibit
  • 9.2 Testing Brighton Connections
  • 9.2.1 Part 1
  • 9.2.2 Part 2
  • 9.2.3 Part 3

    • 10.0 Brighton Timings

  • 10.1 Brighton CFE Timings
  • 10.2 Brighton Processor Interface Timings
  • 10.3 Memory Timing
  • 10.3.1 Abbreviations/Symbols

    • Appendix A. Brighton Pin Name/Number cross reference

  • 11.1 Brighton Pin Names/Numbers (listed by pin name)
  • 11.2 Brighton Pin Names/Numbers (listed by number)

    • Appendix B. Mechanical Drawing

    Appendix C. Acronym Glossary

    Appendix D. References

  • 14.1 Trademarks

    • Preface

    This document describes the function of the Brighton Split Bus/Dual ECC Memory Controller. One bus is an Intel 80960CA interface; the other is a CFE bus interface. The purpose of this specification is to provide a pinout, register description, functional description and timing information.

    0.1 Some Conventions

    0.2 Brighton Overview

    0.2.1 General Description

    The Brighton Split Bus/Dual ECC Memory Controller (Brighton) is a VLSI chip that provides the interface between an Intel 80960CA, a local CFE bus, and two memories. The highest performance will be achieved when the 80960 executable code, data structures, etc. are in instruction memory and the local bus masters are transferring data (communications packets) to and from packet memory.

    0.2.2 Features

    0.2.3 Performance

    On the Intel 80960CA bus the chip will support 3-1-1-1-0 cycles (36 MB/s) to either memory. Up to four word bursts (quad word aligned) will be supported. Brighton will also support 3-1-1-1-1 reads (2-1-1-1-1 writes) from the local bus to packet memory (4-1-1-1-1 to instruction memory). However, the local bus may burst more than four words. This translates to:

    0.2.4 Block Diagrams

    Figure 1. shows a high-level view of how Brighton fits in an overall system. Figure 2. shows a block diagram of Brighton 
                                 +--------------+
                             | INSTRUCTION  |
                             |    MEMORY    |
                             +---+-----+----+
                  +---+          A     A
                  |ROM|     Addr/|     |Data
                  ++-++     Cntl |     V
                   A |       +---+-----+---+
        +--------+ | |       |             |
        |        | | |  Addr |             |
        |        +-+-|------>+             |  32-bit CFE
        |80960CA | | |       |  BRIGHTON   |   interface
        |        | | |       |             +<----------+----------+- - -
        |        | | |  Data |             |           V          V
        |        +<|-+------>+             |       +---+---+  +---+---+
        |        | | |       |             |       |       |  |       |
        +--------+ | |       +---+-----+---+       | CFE   |  | CFE   | . .
                   V V      Addr/|     A           |DEVICE |  |DEVICE |
                  ++-+-+    Cntl |     |Data       +-------+  +-------+
         optional |SRAM|         V     V
                  +----+     +---+-----+----+
                             |    PACKET    |
                             |    MEMORY    |
                             +--------------+
    Figure 1. Block diagram showing major Brighton Interfaces 
       +---------------------------------------------------------+
   |            A            A                               |
   |            V            V                               |
   |     +------+----+  +----+------+     +-----------+      |
   |     |Async Debug|  |Instruction|     | Interrupt +----->|
   |     |    Port   |  |  Memory   |     | Controller|      |
   |     +-----------+  | Interface |     +-----------+      |
   |                    +--+---+--+-+                        |
   |                       A   A  A       +-----------+      |
   |     +-----------+     |   |  +------>+    CFE    |      |
   |     |  80960CA  +<----+   |          | local bus |      |
   |     | Interface |         |          | Interface |      |
   |<--->+           +<--------|--------->+           +<---->|
   |     |    and    |     +---+---+      |    and    |      |
   |     |           |     |Refresh|      |           |      |
   |     |   Task    |     |Control|      | Local bus |      |
   |     |Protection +<-+  +---+---+  +-->+Protection |      |
   |     +-----------+  |      |   |  |   +-----+-----+      |
   |                    +--+   |   +--+         A            |
   |                       |   |   |            V            |
   |                       V   V   V      +-----+-----+      |
   |     +-----------+  +--+---+---++     |    CFE    |      |
   |     |           |  |  Packet   |     | local bus +<---->|
   |     |  Timers   |  |  Memory   |     |  Arbiter  |      |
   |     |           |  | Interface |     |           |      |
   |     +-----------+  +----+------+     +-----------+      |
   |                         |                               |
   |                         V                               |
   +---------------------------------------------------------+
    Figure 2. Major Functional Blocks in Brighton

    0.2.5 Data/Address Paths

    Shown in Figure 3. are the major address and data paths in Brighton. 
                                                 PACKET  MEMORY

                                    DATA                      ADDR
                             +--------+-------+           +----+----+
                             |        |       |           |    |    |
                             |     +--+--+    |           |    |    |
                             |     |     |    |           |    A    |
                             |     A   VVVVV  |           |   AAA   |
                             |    AAA   VVV   |           |  AAAAA  |
                             |   AAAAA   V    |           |    |    |
                             |     |     |    |           |    |    |
                             +-----+-----+----+           +----+----+
                                   A     |                     A
                                   |     +--------+            |
                            +------+---+          |       +----+----+
                            | ecc gen  |          V      /___________\
                            +------+---+    +-----+----+   A A A A A
                                   A        | chk/corr |   | | | | |
                                   |        +---+------+   | | | | |           +---+
                              +----------+      |          | | | | |   +------>+PAR|
                             /____________\     |          | | | | |   |       |CHK+<-+
                                A   A A         |          | | | | |   |       +---+  |
    +----------+                |   | |         |          | | | | |   |              | +-----------+
  A |          |             +--|---|-|---------+----------|-|-|-|-|-+ |              | |     <<    |
  D |   >>     |             |  |   | |                    | | | | | | |       +---+  +-+---<<<<--+ |
  D +--->>>>---+-------------|--|-+-|-|--------------------|-|-|-+ | | |       |PAR|    |     <<  | |
  R |   >>     |             |  | | | |     +----+         | | | | | | |       |GEN|<-+ |         +-+
8   |          |             |  | | | |     |LBUS+---------+ | | | | | |       +---+  | |  >>     | | P  L
0   +----------+             |  | | | +---->|PROT|<----------|-|-|-+ | |          A   +-+-->>>>---+ | A  O
9                        /|  |  | | | |     +----+           | | | | | |      |\  +-+   |  >>       | R  C
6                       / |<-+  | +-|-|---------+  +-------+ | | | | +-|----->| \   |   +-----------+ I  A
0                      |  |     |   | |         |  |REFRESH+-|-+ | |   |      |  |  |                 T  L
C   +-----------+   +--|  |<----|---+ |   +     V  +-------+ | | +-|---|----->|  +--+   +-----------+ Y
A   |       <<  |   |  |  |     |   | +-->|\  +-+-------+    | | | |   | +--->|  |  |   |  >>       |    B
  D | +---<<<<--+<--+   \ |<-+  |   |     | |-|TASK PROT+----+ | | |   | | +->| /   +-->+-->>>>---+ | A  U
  A | |     <<  |        \|  |  |   |  +->|/  +---------+    | | | |   | | |  |/        |  >>     | | /  S
  T +-+         |            |  |   |  |  +                  | | | |   | | |            |         +-+ D
  A | |  >>     |            |  |   |  |                     | | | |   | | |            |     <<  | |
    | +-->>>>---+--------+   |  |   +--|---------------------|-|-|-|---+-|-|------+-----+---<<<<--+ |
    |    >>     |        |   |  |   |  |                     | | | |     | |      |     |     <<    |
    +-----------+        +---|--+---|--|---------------------|-|-|-|-----+ |      |     +-----------+
                             +--|---|--+--------+------------|-|-|-|-------+      |
                                V   V  V        |            | | | |              |
                             +-----------+      |            | | | |              V
                              \_________/       |            | | | |        +------------+
                                   |        +---+------+     | | | +--------+ ADDR LATCH |
                                   V        | chk/corr |     | | | |        +------------+
                           +-------+-+      +-----+----+     V V V V
                           | ecc gen |            A        +---------+
                           +-------+-+            |         \_______/
                                   |     +--------+             |
                                   V     |                      V
                             +-----+-----+----+            +----+----+
                             |     |     |    |            |    |    |
                             |   VVVVV   A    |            |    |    |
                             |    VVV   AAA   |            |  VVVVV  |
                             |     V   AAAAA  |            |   VVV   |
                             |     |     |    |            |    V    |
                             |     +--+--+    |            |    |    |
                             |        |       |            |    |    |
                             +--------+-------+            +----+----+
                                    DATA                       ADDR

                                           INSTRUCTION MEMORY
    Figure 3. Brighton Data/Address Paths

    1.0 Brighton Signal Description

    1.1 80960CA Interface

    The following are the signals used to interface to the 80960CA:

    P_A31:2 I 30-Bit Address--The 80960CA's address is received on these lines. This address is word (4-byte) aligned.
    -P_BE3:0 I Byte Enables--For writes, these signals tell Brighton which byte(s) to write at the selected address. If one or more byte enables are inactive then Brighton will perform a read-modify-write memory cycle. For reads, these bits determine which bytes will be driven on the data bus.
    P_D31:0 I/O 32-Bit Data Bus--32-bit data is communicated between Brighton and the 80690CA on this bus.
    -P_READY O Ready--For 80960CA reads, this signal indicates that data is valid on the rising edge of PCLK (PCLK is the output clock of the 80960CA). For 80960 writes, this signal indicates completion of the write cycle.
    -P_ADS I Address Strobe--This signal indicates to Brighton that a new address cycle is beginning.
    P_W/-R I Write/Read--This signal indicates to Brighton whether a cycle is a write or read access.
    -P_BLAST I Burst Last--This signal indicates the last access of a burst access. This signal must be valid at least one state before data is ready. (This can be accomplished by programming the 80960 for 0 wait states and always letting READY pace the cycle.) See "80960 Region Programming".
    -P_DMA I DMA--This signal is asserted during 80960 DMA accesses. Brighton uses this signal to determine if the current 80960 access is by a task (protection will be checked) or by 80960 DMA (no hardware protection).
    Table 1. 80960CA Interface Signals

    1.2 Local Bus Interface

    The following are the signals used to interface to the local bus:

    L_AD31:0 I/O 32-Bit Multiplexed Address/Data Bus--These lines will contain address information during the address cycle, after which they will be used for data. When Brighton is the master, they will be driven during address and for write data. When Brighton is the selected slave, it will drive these lines with read data.
    L_ADP3:0 I/O Local Bus Parity Bits--When address or data is present on the AD bus, these lines will contain the odd parity of each byte. L_ADP0 corresponds to AD7:0, L_ADP1 to AD15:8, L_ADP2 to AD23:16 and L_ADP3 to AD31:24.
    -L_BE3:0 I/O Byte Enables--Brighton drives these as a master and latches them at address time as a slave. For writes, these signals select which byte(s) to write at the selected address. For reads, these bits determine which bytes will be driven onto data bus.
    -L_READY I/O Ready--For reads, this signal indicates that data is valid on the rising edge of PCLK. For writes, this signal indicates completion of the write cycle. Brighton drives this as a slave and monitors it as a master.
    -L_ADS I/O Address Strobe--This signal indicates that a new address cycle is beginning. Address is on the AD bus during this cycle (L_W/-R and -L_BE0:3 are also latched). Brighton drives this as a master and monitors it as a slave.
    L_W/-R I/O Write/Read--This signal indicates whether a cycle is a write or read access. Brighton drives this as a master and monitors it as a slave. This signal is latched during the address phase.
    -L_BLAST I/O Burst Last--This signal indicates the last access of a burst access. Brighton drives this as a master and monitors it as a slave.
    -LEXCPT I/O Local Bus Exception--Brighton will drive this line for two clocks if Brighton detects a local bus parity error as a slave, a multi-bit ECC error occurs during a local bus access to memory, or a local bus time-out occurs. Brighton monitors this line and will terminate its local bus cycle if this line goes active (must be held active for two clocks).
    -L_REQ2:0 I Local Bus Requests--These signals are used to indicate to Brighton that another master is requesting the local bus. See 5.0 , "Arbiter Function" for details on servicing priority.
    -L_GRANT2:0 O Local Bus Grants--These signals indicate to a local bus master that they have been granted the bus. See 5.0 , "Arbiter Function" for more information. These lines function as inputs when in Manufacturing Test Mode.
    -BRREQ O Brighton Request--When this signal goes low it indicates that Brighton wants to access the local bus. See 5.4 , "Special Arbitration Modes" for more information.
    -BRGNT I Brighton Grant--When this signal goes low it indicates that Brighton has been granted the local bus by an external arbiter. This signal is only monitored when bit 6 of the SPAR is a '1'. See 5.4 , "Special Arbitration Modes" for more information.
    Table 2. Local Bus Interface Signals

    1.3 DRAM Interface

    The following are the signals used to interface to DRAM memories.

    DD31:0/ ID31:0 I/O 32-Bit Packet Data Bus/32-Bit Instruction Data Bus--These lines are used to transfer data to and from memory.
    DCB6:0/ ICB6:0 I/O Packet Memory Check Bits/Instruction Memory Check Bits--These lines are used to transfer error detection/correction codes to and from memory.
    DA11:0/ IA11:0 O 12-Bit Packet DRAM Address/12-Bit Instruction DRAM Address--These lines are used to transfer the row and column address to the DRAM.
    -DRAS1:0/ -IRAS1:0 O Packet RAS/Instruction RAS--These lines are used to strobe the row address into DRAM. In one-bank memories, only RAS0 is used. In two-bank memories, RAS1 is used to access the second bank.
    -DCAS1:0/ -ICAS1:0 O Packet CAS/Instruction CAS--These lines are used to strobe the column address into DRAM. In one-bank memories, only CAS0 is used. In two-bank memories, CAS1 is used to access the second bank.
    -DW/ -IW O Packet Memory Write/Instruction Memory Write--This signal controls whether a read or write is to be performed on memory.
    Table 3. Packet Memory/Instruction Memory Interface Signals

    1.4 Other Interface Signals

    The following are descriptions of all other Brighton signals.

    TXDATA O Transmit Data--This is the data-out pin for the serial debug port.
    RXDATA I Receive Data--This is the data-in pin for the serial debug port.
    BRINT3:0 O Four-Bit Encoded Interrupt--These lines will be used to signal interrupts to the local interrupt controller. See 9.0 , "Interrupt Function" for more details.
    -ROSCS O ROS Chip Select--This line will be active when the 80960CA is accessing an address in the 0-256MB or the 80960 boot record. See Table 10..
    PCLK I Clock Input--This is the clock input to the chip. It will normally be driven by the PCLK output of the Intel 80960CA.
    -PRESET I Power-On-Reset--This line causes all Brighton registers to assume their reset values. All Brighton functions are reset and do not operate until this line is released.
    -MTST I Manufacturing Test--This pin will be used by manufacturing for testing purposes. It is normally pulled high.
    -DI_IN I Driver Inhibit Enable--Used for testing. This pin should be tied HIGH during normal chip operation. If -DI is LOW AND RXDATA is LOW then all off-chip drivers in Brighton are tri-stated. If -DI is LOW AND -POR is LOW Brighton will be in Static-IDD-Test-Mode (used by chip manufacturer).
    A_CLK I LSSD A Clock--Used for chip testing. This pin should be tied HIGH during normal chip operation.
    B_CLK I LSSD B Clock--Used for chip testing. This pin should be tied HIGH during normal chip operation.
    C_CLK I LSSD C Clock--Used for chip testing. This pin should be tied HIGH during normal chip operation.
    Table 4. Other Brighton Signals

    COMP NA Driver Compensation Resistor. This pin should should be pulled-up by a 909 ohm +/- 1% resistor to +5V.
    VCC NA Power pins. All VCC pins must be connected to a +5 volt power plane.
    GND NA Ground pins. All GND pins must be connected to a ground plane.
    Table 5. Brighton Non-signal Pins

    2.0 Brighton Addressable Registers

    The memory locations of all registers addressable in Brighton are shown below. The addresses are valid for both 80960CA and local bus accesses. Detailed information is found in the indicated section. Each register is 4 byte aligned in the address space and should be accessed using 80960 'word' load (ld) and 'word' store (st) instructions (except were noted). Not doing so may cause unexpected results. RESET values are shown in the Reset Condition section for each register. For these sections 'U' = Undefined, and 'S' = value is the SAME as it was prior to the RESET being issued.

    Note: 'x' = timer port # (0-4).

    Table 6. Brighton Addressable Registers
    Register Name Address Type Section
    Timer Control Registers 1FFBx000h r/w 2.1 , "Timer Control Register (TCR0-4)"
    Timer Preset Registers 1FFBx004h r/w 2.2 , "Timer Preset Register (TPR0-4)"
    Timer Present Value Registers 1FFBx008h ro 2.3 , "Timer Present Value register (TPV0-4)"
    Timer Command Registers 1FFBx00Ch r/w 2.4 , "Timer Command Register (TCMD0-4)"
    Transmitter Buffer Port 1FFB8000h r/w 2.5 , "Transmitter Buffer Port (TxBUF)"
    Receiver Buffer Port 1FFB8004h ro 2.6 , "Receiver Buffer Port (RxBUF)"
    Port Configuration Register 1FFB8008h r/w 2.7 , "Port Configuration Register (PCR)"
    Memory Protection Enable Register 1FFB9000h r/w 2.8 , "Memory Protection Enable Register (MPER)"
    Task Page Table Base Register 1FFB9004h r/w 2.9 , "Task Page Table Base Register (TASK_PTBR)"
    Master0 Page Table Base Register 1FFB9008h r/w 2.10 , "Master0 Page Table Base Register (MC_PTBR)"
    Master1 Page Table Base Register 1FFB900Ch r/w 2.11 , "Master1 Page Table Base Register (AM_PTBR)"
    Task Protection Address Trap Register 1FFB9010h ro 2.12 , "Task Protection Address Trap Register (TPATR)"
    Task Protection Status Register 1FFB9014h ro 2.13 , "Task Protection Status Register (TPSTAT)"
    Local Bus Protection Address Trap Register 1FFB9018h ro 2.14 , "Local Bus Protection Address Trap Register (LPATR)"
    Local Bus Protection Status Register 1FFB901Ch ro 2.15 , "Local Bus Protection Status Register (LPSTAT)"
    Exception Address Trap Register 1FFB9020h ro 2.16 , "Local Bus Exception Address Trap Register (LEXATR)"
    Exception Status Register 1FFB9024h ro 2.17 , "Local Bus Exception Status Register (LEXSTAT)"
    Single-bit ECC Address Trap Register 1FFB902Ch ro 2.18 , "Single-bit ECC Error Address Trap Register (SBATR)"
    Single-bit ECC Error Register 1FFB9030h r/w 2.19 , "Single-Bit ECC Error Register (SBECCR)"
    ECC Address Trap Register 1FFB9034h ro 2.20 , "ECC Address Trap Register (ECCATR)"
    ECC Status Register 1FFB9038h ro 2.21 , "ECC Status Register (ECCSTAT)"
    Brighton Gate Array ID 1FFBA000h ro 2.22 , "Gate Array ID Register (GAIDR)"
    Memory Configuration Register 1FFBA004h r/w 2.23 , "Memory Configuration Register (MCR)"
    Special Arbitration Register 1FFBA008h r/w 2.24 , "Special Arbitration Register (SPAR)"
    Local Bus Configuration Register 1FFBA00Ch r/w 2.25 , "Local Bus Configuration Register (LBCFG)"
    Force ECC Error Register 1FFBA010h r/w 2.26 , "Force ECC Error Register (FEER)"

    Note that the registers are grouped into different 4k byte regions depending on their function to allow protection on each area separately.

    2.1 Timer Control Register (TCR0-4)

    Description

    Each timer has a timer control register which specifies timer specific parameters. These are described below.

    Register Format
    (ADDRESS = 1FFBx000h) r/w     x = timer # (0-4)

       7   6   5   4   3   2   1   0
     +---+---+---+---+---+---+---+---+
     |RSV|RSV|RSV|RSV|RSV|INT|ZDC|IEN|
     +---+---+---+---+---+---+---+---+
    Bit Descriptions
    Reset Conditions
            RESET:    0000 0000

    2.2 Timer Preset Register (TPR0-4)

    Description
    Each timer has a preset register which specifies the initial count value for the timer. Each timer is actually a down counter that starts counting when the value of the TPR is loaded into the counter, and a start command is issued. A value of 'FFFF'h causes the maximum of 65,535 ticks to occur before zero count. A value of '0000'h is not allowed. A value of '0001'h causes 1 tick to occur before zero count. TMR 0,1,2,4 are 16-bit timers and TMR 3 is a 24-bit timer. See 7.0 , "Brighton Timers" for 'tick' length.

    Register Format
    (ADDRESS = 1FFBx004h) r/w    x = timer # (0-4)

       23                          0
      +-----------------------------+
      |        Timer Preset         |
      +-----------------------------+
    Bit Descriptions

    Reset Conditions
            RESET:    0000 0000 0000 0000 0000 0000

    2.3 Timer Present Value register (TPV0-4)

    Description
    Each timer can be read to determine its present count value at any time. This can be done without stopping the timer. TPV 0,1,2,4 are 16-bit read only registers and TPV 3 is a 24-bit read only value.

    Register Format
    (ADDRESS = 1FFBx008h) ro    x = timer # (0-4)

       23                          0
      +-----------------------------+
      |      Timer Present Value    |
      +-----------------------------+
    Bit Descriptions

    Reset Conditions
            RESET:    0000 0000 0000 0000 0000 0000

    2.4 Timer Command Register (TCMD0-4)

    Description
    Each timer has a set of three defined commands to start, stop, and preset individual timers. Also, this register can be read to determine if the timer is currently running.

    Register Format
    (ADDRESS = 1FFBx00Ch) r/w    x = timer # (0-4)

       7   6   5   4   3   2   1   0
     +---+---+---+---+---+---+---+---+
     |   |   |   |RUN|   |   |PRE|STR|
     |RSV|RSV|RSV|   |RSV|RSV|   |STP|
     +---+---+---+---+---+---+---+---+
    Bit Descriptions
    Reset Conditions
            RESET:    0000 0000

    2.5 Transmitter Buffer Port (TxBUF)

    Description
    The TxBUF is the port where data is loaded that is to be sent out the serial port. This port is actually a two-deep FIFO + shift register. When the transmitter is empty, a write to this port sends data immediately to the shift register where the shifting operation begins. Bit 8 of this port can then be read to see if the transmit FIFO is full. If not, another write can be performed to FIFO another byte of data. When Bit 8 is set, it means the FIFO is full. An interrupt will be generated to the 80960 when the FIFO again becomes empty (the shift register still has data to shift out at this time).

    Register Format
    (ADDRESS = 1FFB8000h) r/w - byte addressable

   15  14  13  12  11  10  9   8    7           0
 +---+---+---+---+---+---+---+---++--------------+
 |INT|RSV|RSV|RSV|RSV|RSV|RSV|FUL||  TxBUF Port  |
 +---+---+---+---+---+---+---+---++--------------+
      Transmit Status Byte       Transmit Data Byte
    Bit Descriptions
    Reset Conditions
            RESET:    0000 0000 0000 0000

    2.6 Receiver Buffer Port (RxBUF)

    Description
    The RxBUF is the port where data can be read that has been received. This port is actually a two-deep FIFO + shift register. Data that comes in from the serial link is accumulated in the shift register and then sent to the first byte of the FIFO. An interrupt is generated to the 80960 at this point. If there is no available position in the FIFO for the the accumulated byte to be moved, bit 9 of the RxBUF is set. This is equivalent to an overrun condition.

    Register Format
    (ADDRESS = 1FFB8004h) ro - byte addressable

   15  14  13  12  11  10  9   8    7           0
 +---+---+---+---+---+---+---+---++--------------+
 |INT|RSV|RSV|RSV|VAL|MDA|OVR|FRA||  RxBUF Port  |
 +---+---+---+---+---+---+---+---++--------------+
       Receive Status Byte        Receive Data Byte
    Bit Descriptions

    Reset Conditions
            RESET:    0000 0000 0000 0000

    2.7 Port Configuration Register (PCR)

    Description
    The PCR is used to enable operation of the serial debug port and program its features.

    Register Format
    (ADDRESS = 1FFB8008h) r/w

    7   6   5   4   3   2   1   0
  +---+---+-------+---+---+---+---+
  |RSV|RSV| BAUD  |IEN|WRP|REN|TEN|
  +---+---+-------+---+---+---+---+
    Bit Descriptions
    Reset Conditions
            RESET:    0000 0000

    2.8 Memory Protection Enable Register (MPER)

    Description
    This register provides the capability to turn memory protection on and off separately for the various regions in the memory map. It also provides the capability to turn protection on and off for tasks, Master1 and Master0 interfaces. A kernel will normally execute without RAM/IO protection, and device drivers and interrupt handlers would execute with or without protection at their option. See 6.0 , "Memory Protection" for more information.

    This register is NOT protected by the hardware. When writing this register, the upper 16 bits serve as a mask for the lower 16 bits. For example, if you wanted to turn on the 960 task protection bit you would store the word x'00028002'. This tells Brighton: write the register (bit 15=1), write bit 1 (bit 17=1) and set bit 1 to a 1 (bit 1=1). The mask bits always read 0's. Bit 15 must be a '1' to write this register. This register can only be written using 32-bit writes (i.e. all bytes enabled).

    For protection to be enabled for a particular access, all bits/signals relating to that access must be in the correct state. (i.e. For a DRAM read from the 80960: 960TSK=1, ALLRD=1, RAMIO=1 and the -PDMA signal is HIGH.)

    Register Format

    (ADDRESS = 1FFB9000h) r/w 

    Mask bits  31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16

Data bits  15  14  13  12  11  10   9   8   7   6   5   4   3   2   1   0
          +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
          |WRT|   |   |   |   |   |   |   |RAM|UP |ALL|LB |MST|MST|960|LOW|
          |EN |RSV|RSV|RSV|RSV|RSV|RSV|RSV|IO |MEM|RD |MEM| 0 | 1 |TSK|MEM|
          +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    Reset Conditions
     RESET:    0000 0000 0000 0000 0000 0000 0000 0000

    2.9 Task Page Table Base Register (TASK_PTBR)

    Description
    This register (which is normally changed by supervisory level software at task switch time) is a pointer to the starting address of a task's page table. Logic interprets all writes to this register as a task switch, and invalidates all entries in the task page-access-byte cache. The six least significant bits of this register will always read '0'. See 6.0 , "Memory Protection". Task protection tables must be in instruction memory if it is installed.

    Register Format

    ADDRESS = 1FFB9004h (r/w) 

      31                6 5      0
 +-------------------+--------+
 |     TASK_PTBR     | 000000 |
 +-------------------+--------+
    Reset Conditions
     RESET:    SSSS SSSS SSSS SSSS SSSS SSSS SS00 0000

    2.10 Master0 Page Table Base Register (MC_PTBR)

    Description
    This register (which is normally managed by the supervisory level software) is a pointer to the starting address of the Master0 interface page table. A write to this register invalidates all entries in the Master0 page-access-byte cache. The six least significant bits of this register will always read '0'. See 6.0 , "Memory Protection". Master0 protection tables must be in packet memory.

    Register Format

    (ADDRESS = 1FFB9008h) r/w 

      31                6 5      0
 +-------------------+--------+
 |       MC_PTBR     | 000000 |
 +-------------------+--------+
    Reset Conditions
     RESET:    SSSS SSSS SSSS SSSS SSSS SSSS SS00 0000

    2.11 Master1 Page Table Base Register (AM_PTBR)

    Description
    This register (which is normally managed by the supervisory level software) is a pointer to the starting address of the Master1 page table. A write to this register invalidates all entries in the Master1 page-access-byte cache. The six least significant bits of this register will always read '0'. See 6.0 , "Memory Protection". Master1 protection tables must be in packet memory.

    Register Format

    (ADDRESS = 1FFB900Ch) r/w 

      31  30            6 5      0
 +---+---------------+--------+
 | 0 |   AM_PTBR     | 000000 |
 +---+---------------+--------+
    Reset Conditions
     RESET:    0SSS SSSS SSSS SSSS SSSS SSSS SS00 0000

    2.12 Task Protection Address Trap Register (TPATR)

    Description
    This register latches the address that caused a memory protection violation by an 80960 task. An interrupt is generated. Once the register has trapped an address it is locked and will not trap any subsequent failures until the TPSTAT is read. The data is valid until the TPSTAT is read.

    Note: The TPATR register should be read BEFORE reading the TPSTAT.

    Register Format

    (ADDRESS = 1FFB9010h) ro 

      31                  0
 +---------------------+
 |       TPATR         |
 +---------------------+
    Reset Conditions
     RESET:    UUUU UUUU UUUU UUUU UUUU UUUU UUUU UU00

    2.13 Task Protection Status Register (TPSTAT)

    Description
    This register latches the status associated with a memory protection violation by an 80960 task. An interrupt is generated. Once the register has trapped status it is locked and will not trap any subsequent failures until the TPSTAT is read.

    Note: The TPSTAT register should be read AFTER reading the TPATR.

    Register Format

    (ADDRESS = 1FFB9014h) ro 

      31    8   7   6   5   4   3   2   1   0
 +--------+---+-------+---+---+---+---+---+
 |  RSV   |LCK|  RSV  |PWR|PBE|PBE|PBE|PBE|
 |        |   |       |   | 3 | 2 | 1 | 0 |
 +--------+---+-------+---+---+---+---+---+

RSV = reserved
    Bit Descriptions

    Reset Conditions
     RESET:    0000 0000 0000 0000 0000 0000 0UUU UUUU

    2.14 Local Bus Protection Address Trap Register (LPATR)

    Description
    This register latches the address that caused a local bus (Master0 or Master1) memory protection violation. An interrupt is generated. Once the register has trapped an address it is locked and will not trap any subsequent failures until BOTH local bus protection interrupts are cleared. Bits in the LPSTAT indicate whether the address trapped is for Master0 protection or Master1 protection. The LPATR is valid until the LPSTAT is cleared.

    Register Format

    (ADDRESS = 1FFB9018h) ro 

      31                  0
 +---------------------+
 |       LPATR         |
 +---------------------+
    Reset Conditions
     RESET:    UUUU UUUU UUUU UUUU UUUU UUUU UUUU UUUU

    2.15 Local Bus Protection Status Register (LPSTAT)

    Description
    This register latches the status associated with a local bus (Master0 or Master1) protection violation. An interrupt is generated. Once the register has trapped status it is locked and will not trap any subsequent failures until the LPSTAT is read. This register is byte addressable. When clearing interrupts, writes should be byte writes. The LPSTAT register should be cleared AFTER reading the LPATR.

    Register Format

    (ADDRESS = 1FFB901Ch) ro - byte addressable 

      31   11  10   9    8    7   3   2    1    0
 +-------+----+----+----+-------+----+----+----+
 |  RSV  |LWR1|ATR1|MST1|  RSV  |LWR0|ATR0|MST0|
 +-------+----+----+----+-------+----+----+----+

RSV = reserved
    Bit Descriptions

    Reset Conditions
     RESET:    0000 0000 0000 0000 0000 0UU0 0000 0UU0

    2.16 Local Bus Exception Address Trap Register (LEXATR)

    Description
    This register latches the address that caused a local bus exception error (or parity error when Brighton is the master). Once the register has trapped an address it is locked and will not trap any subsequent failures until the LEXSTAT is cleared (all three parts). The address is only valid if the corresponding bits in the LEXSTAT are valid and until the LEXSTAT is cleared.

    Note: When trapping the address for a data parity error (Brighton master), the address trapped in the LEXATR will be the address of the error + 4h.

    Register Format

    (ADDRESS = 1FFB9020h) ro 

      31                  0
 +---------------------+
 |      LEXATR         |
 +---------------------+
    Reset Conditions
     RESET:    UUUU UUUU UUUU UUUU UUUU UUUU UUUU UUUU

    2.17 Local Bus Exception Status Register (LEXSTAT)

    Description
    This register latches the status associated with a local bus exception (or a parity error when Brighton is the master). The register is divided into three parts, status for: LEXCPT seen with Brighton master (MEX), Brighton detects a local bus parity error while doing a read (MPE), and LEXCPT sourced by Brighton (EXS). The three parts operate independently but share the LEXATR register. Once a part has trapped status it is locked and will not trap any subsequent failures until the interrupt is cleared. If none of the 'parts' were locked at the time of the error then the address will also be trapped in the LEXATR. Status bits are only valid if the corresponding pending (PND) bit is set. To clear pending interrupts and unlock a part, write a '1' to the corresponding pending (PND) bit. Byte writes are NOT supported.

    The EXS part does NOT correspond to a Brighton interrupt. It is expected that the master that received the exception sourced an interrupt to the processor.

    Register Format

    (ADDRESS = 1FFB9024h) ro 

      31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16
 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
 |RSV|RSV|RSV|RSV|MEX|MEX|MEX|MEX|RSV|RSV|RSV|RSV|RSV|MPE|MPE|MPE|
 |   |   |   |   |ATR|WR |DMA|PND|   |   |   |   |   |ATR|DMA|PND|
 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+

  15  14  13  12  11  10   9   8   7   6   5   4   3   2   1   0
 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
 |RSV|MST|MST|MST|960|960|EXS|EXS|LTO|RSV|RSV|SLV|ECC|RSV|LAP|EXS|
 |   | 2 | 1 | 0 |DMA|   |WR |ATR|   |   |   |PAR|   |   |ERR|PND|
 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+

RSV = reserved
    Bit Descriptions
    Reset Conditions
     RESET:    UUUU UUU0 UUUU UUU0 UUUU UUUU UUUU UUU0

    2.18 Single-bit ECC Error Address Trap Register (SBATR)

    Description
    This register latches the address that caused a single-bit ECC error interrupt. The contents of this register are locked and valid until the interrupt is cleared.

    Register Format

    (ADDRESS = 1FFB902Ch) ro 

      31               2 10
 +------------------+--+
 |       SBATR      |00|
 +------------------+--+
    Reset Conditions
     RESET:    UUUU UUUU UUUU UUUU UUUU UUUU UUUU UU00

    2.19 Single-Bit ECC Error Register (SBECCR)

    Description
    This register is used to count the number of single-bit ECC errors detected by Brighton. The SBECCR holds an 8-bit value that is decremented each time a single-bit ECC error is detected by Brighton. When the count reaches zero an interrupt is generated. To clear the interrupt, write a non-zero value to the SBECCR.

    Register Format

    (ADDRESS = 1FFB9030h) r/w 

       7              0
 +------------------+
 |      SBECCR      |
 +------------------+

    Reset Conditions
     RESET:    1111 1111

    2.20 ECC Address Trap Register (ECCATR)

    Description
    This register latches the address that caused the last multi-bit ECC error caused by an 80960 or task protection access. The register will be locked and valid until the interrupt is cleared by reading the ECCSTAT.

    Register Format

    (ADDRESS = 1FFB9034h) ro 

      31              2 10
 +-----------------+--+
 |       ECCATR    |00|
 +-----------------+--+
    Reset Conditions
     RESET:    UUUU UUUU UUUU UUUU UUUU UUUU UUUU UU00

    2.21 ECC Status Register (ECCSTAT)

    Description
    This register latches the status associated with a multi-bit ECC error during an 80960 or task protection access. An interrupt is generated. Once the register has trapped status for a multi-bit error it is locked and will not trap any subsequent failures until it is read.

    Register Format

    (ADDRESS = 1FFB9038h) ro 

      31     5  4   3   2   1   0
 +--------+---+---+---+---+---+
 |  RSV   |TSK|960|PWR|LCK|RSV|
 |        |PRO|DMA|   |   |   |
 +--------+---+---+---+---+---+

RSV = reserved
    Bit Descriptions

    Reset Conditions
     RESET:    0000 0000 0000 0000 0000 0000 UUUU UU00

    2.22 Gate Array ID Register (GAIDR)

    Description
    This register will contain the revision level of Brighton.

    Table 7. Brighton GAIDR Values
    Chip Pass GAIDR Value
    1 0x00000001
    2 0x00000002
    All Other Values Reserved

    Register Format

    (ADDRESS = 1FFBA000h) ro 

      31                 0
 +--------------------+
 |       GAIDR        |
 +--------------------+
    Reset Conditions
     RESET:    See Table above.

    2.23 Memory Configuration Register (MCR)

    Description
    This register tells Brighton the amount of packet memory and/or instruction memory that is installed. This register also selects where instruction memory resides in the memory map and the input oscillator speed.

    Register Format
    (ADDRESS = 1FFBA004h) r/w - byte addressable 
      15  14  13  12  11  10   9   8   7   6   5   4   3   2   1   0
 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
 |IM |IM |   |   |   |IM |IM |IM |PM |REF|OSC|   |   |PM |PM |PM |
 |INS|LOC|RSV|RSV|RSV|SZ2|SZ1|SZ0|INS|   |25 |RSV|RSV|SZ2|SZ1|SZ0|
 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    Note: RSV=Reserved, MUST be set to '0'

    Bit Descriptions

    Reset Conditions
     RESET:    1000 0101 1100 0101

    2.24 Special Arbitration Register (SPAR)

    Description
    This register is used to determine whether Brighton is in regular arbitration mode or 'special' arbitration mode. (See 5.4 , "Special Arbitration Modes" for details on usage.) It can also be used to determine the amount of instruction and/or packet memory bandwidth allocated to the 80960. If local bus masters are capable of long burst transfers, this register allows the 80960 to 'sneak in' to memory while the local bus is held 'NOT READY'.

    Register Format

    (ADDRESS = 1FFBA008h) r/w 

     +---+---+---+-------+---+---+---+-------+
 |15 |14 |13 | 12-8  | 7 | 6 | 5 |  4-0  |
 +---+---+---+-------+---+---+---+-------+
 |RSV|IEN|RSV| ICNT  |LTO|PEN|RSV| PCNT  |
 +---+---+---+-------+---+---+---+-------+
    Note: RSV=Reserved

    Bit Descriptions

    Reset Conditions
     RESET:    0000 0000 0000 0000

    2.25 Local Bus Configuration Register (LBCFG)

    Description
    This register specifies how certain local bus functions operate.

    Register Format
    (ADDRESS = 1FFBA00Ch) r/w - byte addressable 
     +-----+------+---+---+---+---+-----+------+
 |31-13|  12  |11 |10 | 9 | 8 | 7-1 |  0   |
 +-----+------+---+---+---+---+-----+------+
 | RSV |BAPAR |BP3|BP2|BP1|BP0| RSV |PARCHK|
 +-----+------+---+---+---+---+-----+------+
    Note: RSV=Reserved

    Bit Descriptions

    Reset Conditions
     RESET:    0000 0000 0000 0000 0000 0000 0000 0000

    2.26 Force ECC Error Register (FEER)

    Description
    This register is used by diagnostics to force bad ECC codes to be written to memory. This register should be set to all 0's for normal operation. A '1' in any of the defined bits will cause the corresponding check bit to be inverted (wrong) when a write occurs to memory. For example, to force a single bit error for data bit 14 (db14) in packet memory, set PCB(6:0)='1011000'. If you now write x'0000 0000' to any location in packet memory, it will read back x'0000 4000' (bit 14 has been 'corrected'). See Figure 4..

    This register also allows you to turn off ECC --the check bits are still written but are not checked on reads-- and to read the most recently read check bits.

    Warning!
    Setting the PCB or ICB bits can be dangerous. Do not allow interrupts, stack usage, DMA, etc. while these bits are set. Also, after clearing these bits re-write the memory that was written while they were set.

    Register Format

    (ADDRESS = 1FFBA010h) r/w - byte addressable 

      31  30  . . . 24  23  22  . . . 16
 +---+-------------+---+------------+
 |   | ICBIN 6:0   |   | PCBIN 6:0  |
 |RSV|             |RSV|            |
 +---+-------------+---+------------+

  15  14  13  12  11  10   9   8   7   6   5   4   3   2   1   0
 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
 | I |ICB|ICB|ICB|ICB|ICB|ICB|ICB| P |PCB|PCB|PCB|PCB|PCB|PCB|PCB|
 |OFF| 6 | 5 | 4 | 3 | 2 | 1 | 0 |OFF| 6 | 5 | 4 | 3 | 2 | 1 | 0 |
 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
    Bit Descriptions

    Reset Conditions
     RESET:    0UUU UUUU 0UUU UUUU 0000 0000 0000 0000



    +-----------+--------+------+------+------+------+------+------+------+
|           |        |      |      |      |      |      |      |      |
|  FEER     |        |      |      |      |      |      |      |      |
|   CB     6|   0    |   0  |   0  |   0  |   1  |   1  |   1  |   1  |
|  value   5|   0    |   0  |   1  |   1  |   0  |   0  |   1  |   1  |
|          4|   0    |   1  |   0  |   1  |   0  |   1  |   0  |   1  |
| 3 2 1 0   |        |      |      |      |      |      |      |      |
+-----------+--------+------+------+------+------+------+------+------+
| 0 0 0 0   |no error| cb4  | cb5  |      | cb6  |      |      | db20 |
+ ----------+--------+------+------+------+------+------+------+------+
| 0 0 0 1   | cb0    |      |      | db26 |      | db28 | db15 |      |
+-----------+--------+------+------+------+------+------+------+------+
| 0 0 1 0   | cb1    |      |      | db4  |      | db29 | db27 |      |
+-----------+--------+------+------+------+------+------+------+------+
| 0 0 1 1   |        | db13 | db0  |      | db18 |      |      |      |
+-----------+--------+------+------+------+------+------+------+------+
| 0 1 0 0   | cb2    |      |      | db12 |      | db30 | db7  |      |
+-----------+--------+------+------+------+------+------+------+------+
| 0 1 0 1   |        |      | db24 |      | db2  |      |      |      |
+-----------+--------+------+------+------+------+------+------+------+
| 0 1 1 0   |        |      | db16 |      | db5  |      |      |      |
+-----------+--------+------+------+------+------+------+------+------+
| 0 1 1 1   | db8    |      |      |      |      |      |      |      |
+-----------+--------+------+------+------+------+------+------+------+
| 1 0 0 0   | cb3    |      |      | db17 |      | db14 | db31 |      |
+-----------+--------+------+------+------+------+------+------+------+
| 1 0 0 1   |        | db1  | db25 |      | db10 |      |      |      |
+-----------+--------+------+------+------+------+------+------+------+
| 1 0 1 0   |        | db9  | db22 |      | db23 |      |      |      |
+-----------+--------+------+------+------+------+------+------+------+
| 1 0 1 1   | db3    |      |      |      |      |      |      |      |
+-----------+--------+------+------+------+------+------+------+------+
| 1 1 0 0   |        | db6  | db11 |      | db19 |      |      |      |
+-----------+--------+------+------+------+------+------+------+------+
| 1 1 0 1   |        |      |      |      |      |      |      |      |
+-----------+--------+------+------+------+------+------+------+------+
| 1 1 1 0   | db21   |      |      |      |      |      |      |      |
+-----------+--------+------+------+------+------+------+------+------+
| 1 1 1 1   |        |      |      |      |      |      |      |      |
+-----------+--------+------+------+------+------+------+------+------+
    Figure 4. Brighton FEER Values

    Each box shows the data bit (db) or check bit (cb) that will appear to be in error.

    Blanks in the table indicate multi-bit errors. (data with mutli-bit errors will be unpredictable)

    3.0 Memory Controller(s)

    3.1 Memory Organization and Addressing

    Brighton supports up to two DRAM memories. These are known as packet memory and instruction memory. The controllers for them are identical. The memory organization supported is the same as the Austin Workstation SIMM. The two bank organization is shown below: 
                         +-----------+
                 +---+A11-0      |
 RAS0------------|---+RAS        |
 CAS0------------|---+CAS  DQ39:0+---+
              +--|---+-W         |   |
 A11-0--------|--+   +-----------+   |
              |  |                   +-----DQ39:0
 -W-----------+  |   +-----------+   |
              |  +---+A11-0      |   |
 RAS1---------|------+RAS        |   |
 CAS1---------|------+CAS  DQ39:0+---+
              +------+-W         |
                     +-----------+
    Note: Brighton only uses 39 of the 40 bits.

    The address is multiplexed to the DRAM as follows:

    DRAM Address 80960CA or Local Bus Address COL ROW
    0 A2 A11
    1 A3 A12
    2 A4 A13
    3 A5 A14
    4 A6 A15
    5 A7 A16
    6 A8 A17
    7 A9 A18
    8 A10 A19
    9 A20 A21
    10 A23 A22
    11 --- A23

    3.2 Memory Size

    Each memory may be 0, 1, 2, 4, 8, 16 or 32 megabytes in size. This is selected by programming the SZ bits in the MCR (see 2.23 , "Memory Configuration Register (MCR)") to the appropriate value. The starting address for packet memory is 512MB (2000 0000h). Instruction memory begins at 564MB or 576MB (2200 0000h or 2400 0000h). See 2.23 , "Memory Configuration Register (MCR)".

    3.3 Memory Speed

    Brighton supports 80/85 ns DRAM. See 10.3 , "Memory Timing".

    3.4 Memory Map

    3.4.1 80960 Memory Map

    From the 80960, the memory map looks as follows:

    FROM TO MPER bits Comments
    00000000 0FFFFFFF 960TSK LOWMEM ROS chip select. Not translated to local bus.
    10000000 1FEFFFFF 960TSK LOWMEM Translated to local bus.
    1FF00000 1FFAFFFF 960TSK RAMIO ALLRD Translated to local bus.
    1FFB0000 1FFBFFFF 960TSK RAMIO ALLRD Not translated to local bus. Brighton IO area.
    1FFC0000 1FFFFFFF 960TSK RAMIO ALLRD Translated to local bus.
    20000000 xxxxxxxx 960TSK RAMIO ALLRD Not translated to local bus. Packet memory area. Address range determined by size of memory (21FFFFFF for 32MB).
    22000000 or 24000000 xxxxxxxx 960TSK RAMIO ALLRD Not translated to local bus. Instruction memory area. Starting address determined by MCR_IMLOC (2.23 , "Memory Configuration Register (MCR)"). Address range determined by size of memory.
    xxxxxxxx 7FFFFFFF 960TSK LBMEM ALLRD Translated to local bus. Local bus memory area. Covers ALL addresses from 20000000 to 7FFFFFFF except where packet and instruction memory are.
    80000000 FFFFFFFF 960TSK UPMEM Not translated to local bus. From x'FFFFFF00' to x'FFFFFF2F' causes a ROSCS.
    Table 10. 80960 Memory Map

    80960 Region Programming

    The 80960 should be programmed to ignore READY from x'00000000' to x'0FFFFFFF' and x'80000000' to x'FFFFFFFF' because Brighton does not drive READY for these addresses. The other regions must be programmed for zero wait states (all cases). Region 1 (x'10000000' to x'1FFFFFFF') should be set to non-burst.

    3.4.2 Local Bus Memory Map

    From the local bus, the memory map looks as follows:

    FROM TO MPER bits Comments
    00000000 1FEFFFFF MST0 MST1 LOWMEM Protection checking only.
    1FF00000 1FFAFFFF
    		No protection checking.
    1FFB0000 1FFBFFFF
    		No protection checking. Brighton register area.
    1FFC0000 1FFFFFFF
    		No protection checking.
    20000000 xxxxxxxx MST0 MST1 ALLRD Packet memory area. Address range determined by size of memory (21FFFFFF for 32MB).
    22000000 24000000 xxxxxxxx MST0 MST1 ALLRD Instruction memory area. Starting address determined by MCR_IMLOC (2.23 , "Memory Configuration Register (MCR)"). Address range determined by size of memory.
    xxxxxxxx 7FFFFFFF MST0 MST1 LBMEM Local bus memory area. Covers ALL addresses from 20000000 to 7FFFFFFF except where packet and instruction memory are.
    80000000 FFFFFFFF MST0 MST1 UPMEM Protection checking only.
    Table 11. Local Bus Memory Map

    3.5 Error Correction Code (ECC)

    The Error Detection and Correction (EDC) code used is a basic one-bit correct, two-bit detect scheme. If the data and check bits are grouped as shown below, chip-kill-detection is achieved (for memory using four-bit wide chips). The all 0's and all 1's condition will also be detected (SIMM-kill-detection).

    For chip-kill-detection, the data and check bits should be grouped as follows:

    The check bits are generated by 'XNOR'ing the indicated data bits (similar to generating odd parity). The data bits used to generate each check bit are shown in Figure 5.. 

     +-----+---------------------------------------------------------------+
 |     |                   Data bit                                    |
 |     +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 |check|3|3|2|2|2|2|2|2|2|2|2|2|1|1|1|1|1|1|1|1|1|1| | | | | | | | | | |
 |bit  |1|0|9|8|7|6|5|4|3|2|1|0|9|8|7|6|5|4|3|2|1|0|9|8|7|6|5|4|3|2|1|0|
 +-----+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 |cb6  |x|x|x|x|x| | | |x| | |x|x|x| | |x|x| | | |x| | |x| |x| | |x| | |
 +-----+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 |cb5  |x| | | |x|x|x|x| |x| |x| | |x|x|x| | |x|x| | | |x| | |x| | | |x|
 +-----+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 |cb4  | |x|x|x| |x| | | | | |x| | |x| | |x|x|x| | |x| | |x| |x| | |x| |
 +-----+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 |cb3  |x| | | | | |x| |x|x|x| |x| |x| | |x| | |x|x|x| | |x| | |x| |x| |
 +-----+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 |cb2  | |x| | | | | |x| | |x| |x| | |x| | | |x|x| | |x|x|x|x| | |x| | |
 +-----+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 |cb1  | | |x| |x| | | |x|x|x| | |x| |x| | |x| | | |x|x| | |x|x|x| | |x|
 +-----+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 |cb0  | | | |x| |x|x|x| | | | | |x| | |x| |x| | |x| |x| | | | |x|x|x|x|
 +-----+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
    Note: An 'x' denotes that this data bit is part of the XNOR tree
    for that check bit.
    Figure 5. Brighton Check-Bit Generation

    The check bits are generated and written to memory at the same time as the data. When the location is read, the data and check bits flow through an XOR tree (same bits as generating logic plus the check bit). This produces seven syndrome bits. These syndrome bits are decoded to determine if and where an error has occurred.

    3.5.1 ECC Errors

    For single-bit errors, Brighton will correct the data on the fly (with no delay) going to the requesting device. Single-bit errors are counted and an interrupt is generated at terminal count (see 2.19 , "Single-Bit ECC Error Register (SBECCR)"). For multi-bit errors the data may be scrambled. Multi-bit errors on 80960 accesses will cause an interrupt. Hardware scrubbing will not be performed.

    ECC errors can be forced (or turned off) using the FEER (see 2.26 , "Force ECC Error Register (FEER)").

    4.0 Local Bus Accesses by Brighton

    Brighton will request the local bus (unless prevented by protection) when the 80960 accesses an address from x'1000 0000' to x'7FFF FFFF' except for the areas where Brighton registers (x'1FFB XXXX'), packet memory and instruction memory are located. The area from x'1000 0000' to x'1FFF FFFF' (except X'1FFB xxxx') is called 'local bus IO'. The area from x'2000 0000' to x'7FFF FFFF' (minus packet and instruction memory) is called 'local bus memory'. (See 2.8 , "Memory Protection Enable Register (MPER)" for register settings to allow access to local bus memory and local bus IO.)

    Brighton will also cause a local bus preempt (but not do a cycle) if:

    This will continue until the 80960 is granted the local bus at which point it will access the local bus. The effect is to make the local bus arbiter the arbiter for packet memory when multiple masters need access to packet memory.

    Only single word (or sub-word) accesses are supported.

    For timings and diagrams, see 10.1 , "Brighton CFE Timings".

    5.0 Arbiter Function

    5.1 Packet Memory Arbiter

    The requesters for the packet memory and their service priority (not round-robin) are :
    1. Refresh
    2. Task Protection Unit (only if instruction memory not installed)
    3. Local Bus Protection Unit
    4. Local Bus (But, see 5.4 , "Special Arbitration Modes")
    5. 80960CA request (But, see 5.4 , "Special Arbitration Modes" and 4.0 , "Local Bus Accesses by Brighton")

    5.2 Instruction Memory Arbiter

    The requesters for the instruction memory and their service priority (not round-robin) are:
    1. Refresh
    2. Task Protection Unit (if Instruction memory installed)
    3. 80960CA request
    4. Local Bus
    The 80960 is the default grantee to both memories.

    5.3 Local Bus Arbiter

    There are four requesters for the local bus: The service order (in round-robin fashion) is (assuming all are constantly requesting):

    Note that an 80960CA request is actually the 80960 starting an address cycle (HOLD and HOLDA are NOT used by Brighton). All other requesters first request the bus, then are granted the bus, then start their address cycle. Since the 80960CA is 'quickest' to the bus, it is the default grantee if there are no other requesters.

    A master will not be granted the bus twice in a row unless there are no other requesters.

    5.3.1 Preemption

    To maximize the bandwidth of the local bus, there is a mechanism for notifying the bus owner that another master is requesting the bus. This is accomplished by removing the GRANT signal from the local bus owner. It is then the current owner's responsibility to finish his cycle and remove his REQUEST. The amount of time the master may remain the bus owner after being preempted is not defined. This is illustrated in the following picture. Two local bus masters are shown (1 and 2). Master1 currently owns the bus.

    1. Master2 requests the bus.

    2. Brighton signals master1 that another master is requesting the bus by removing GNT1.

    3. Master1 is finishing his request (he is not REQUIRED to finish). He releases REQ1 at the same time as asserting BLAST.

    4. READY is asserted for the current (last) data cycle. After seeing READY Master1 may (and does) re-request the bus on the next cycle. (cycle )

    5. Master2 is granted the bus.

    6. Master2 asserts ADS (required at this cycle to maximize data bandwidth but may take longer).

    7. GNT2 is deasserted the state after ADS is detected since another master is requesting the bus. 
                |  1  |  2  |  3  |  4  |  5  |  6  |  7  |
       =====================================================
            +--+  +--+  +--+  +--+  +--+  +--+  +--+  +-
     PCLK   |  |  |  |  |  |  |  |  |  |  |  |  |  |  |
            +  +--+  +--+  +--+  +--+  +--+  +--+  +--+
            |     |     |     |     |     |     |     |
     ___    -------------------------------+    |+-------
     ADS    |     |     |     |     |     ||    ||    |
            |     |     |     |     |     |+-----+    |
            |     |     |     |     |     |     |     |
     _____  -------+    |+-----+    |+-------------------
     READY  |     ||    ||    ||    ||    |     |     |
            |     |+-----+    |+-----+    |     |     |
            |     |     |     |     |     |     |     |
     _____  -------------+    |     |+-------------------
     BLAST  |     |     ||    |     ||    |     |     |
            |     |     |+-----------+    |     |     |
            |     |     |     |     |     |     |     |
     ____   |     |     |+-----------+    |     |     |
     REQ1   |     |     ||    |     ||    |     |     |
            -------------+    |     |+-------------------
            |     |     |     |     |     |     |     |
     ____   |     |+-------------------------------------
     GNT1   |     ||    |     |     |     |     |     |
            -------+    |     |     |     |     |     |
            |     |     |     |     |     |     |     |
     ____   -+    |     |     |     |     |     |     |
     REQ2   ||    |     |     |     |     |     |     |
            |+-------------------------------------------
            |     |     |     |     |     |     |     |
     ____   -------------------------+    |     |+-------
     GNT2   |     |     |     |     ||    |     ||    |
            |     |     |     |     |+-----------+    |
    Figure 6. Local Bus Arbitration and Preempt Mechanism

    5.4 Special Arbitration Modes

    If a local bus master is bursting to/from instruction memory, the 80960 will be prevented from accessing it until the instruction memory arbiter re-arbitrates for the memory. Assuming the local bus is doing a very long burst, re-arbitration will not take place unless a refresh cycle is necessary or the local bus burst crosses a page boundary. The 80960 could be held off for 3 us. (3 us is the time it takes a master to burst 512 words to Brighton memory.) The SPAR may be used to reduce this time. If enabled (IEN=1), Brighton will count the number of cycles a local bus master has done since the 80960 requested instruction memory. When this count equals the programmed value (ICNT), Brighton will force rearbitration for instruction memory and the 80960 will receive access (80960 has higher priority to instruction memory). During this time, the local bus master will be held NOT READY.

    The SPAR is used in very much the same way for packet memory with the following exceptions:

    5.5 Local Bus Timeout

    Brighton contains timer circuitry that is intended to prevent the local bus from hanging. Brighton counts clocks during local bus cycles. The timer starts with an ADS or READY and is reset by READY. If the 64 clocks are counted then Brighton causes a local bus EXCEPTION. This function can be disabled (see LTO bit, 2.24 , "Special Arbitration Register (SPAR)").

    6.0 Memory Protection

    Brighton will provide memory protection hardware external to the 80960 that allows for 80960 processes (tasks) and local bus devices. For tasks, the protection covers IO (x'1FFx xxxx'), packet memory and instruction memory. Master0 protection and Master1 protection cover instruction and packet memory.

    Associated with each executable task are memory resident structures called page tables. Pages are defined to be 4KB in length.

    6.1 Page Table Entries

    Each page table entry covers a 64KB area, which is subdivided into 16-4KB pages. 
      31 30 29 28 . . . 3  2  1  0
 +--+--+--+--+     +--+--+--+--+
 |WR|RD|WR|RD|. . .|WR|RD|WR|RD|
 +--+--+--+--+     +--+--+--+--+
   \ /   \ /         \ /   \ /
    |     |           |     +-- First  4KB page
    |     |           +-------- Second 4KB page
    |     |                        .    .    .
    |     |                        .    .    .
    |     +-------------------- 15th   4KB page
    +-------------------------- 16th   4KB page
    Figure 7. Page Table Entry Format

    WR RD Meaning
    0 0 Inaccessible
    0 1 Read Only
    1 0 Write Only
    1 1 Read/Write
    Table 12. Page Access Bit Definition

    The access bits are checked by hardware on each protected access and an interrupt is generated and the violating address latched if a violation is detected. (see 2.12 , "Task Protection Address Trap Register (TPATR)" or 2.14 , "Local Bus Protection Address Trap Register (LPATR)"). Also, in the case of a write violation, the write to memory will be blocked by the hardware. On 80960 accesses to the local bus, Brighton will prevent the local bus cycle unless the access is allowed by protection.

    6.2 Page Tables

    Page table length is based on the amount of memory installed. Page tables must start on a 64 byte boundary in memory. Page table entries are 32-bits wide and cover 16-4KB pages. Examples of a task page table and local bus page table are shown in Figure 8.. 
             TASK TABLE                             Master0 TABLE

    TASK_PTBR = 20000000                     MC_PTBR = 20000400
                      addresses                               addresses
address     data       covered          address     data       covered
         +--------+                              +--------+
20000000 |00000000| 1FF00000-1FF0FFFF   20000400 |00000000| 20000000-2000FFFF
         +--------+                              +--------+
20000004 |00000000| 1FF10000-1FF1FFFF   20000404 |00000000| 20010000-2001FFFF
         +--------+                              +--------+
20000008 |00000000| 1FF20000-1FF2FFFF   20000408 |00000000| 20020000-2002FFFF
         +--------+                              +--------+
2000000C |00000000| 1FF30000-1FF3FFFF   2000040C |00000000| 20030000-2003FFFF
         +--------+                              +--------+
20000010 |00000000| 1FF40000-1FF4FFFF   20000410 |00000000| 20040000-2004FFFF
         +--------+                              +--------+
20000014 |00000000| 1FF50000-1FF5FFFF   20000414 |00001540| 20050000-2005FFFF
         +--------+                              +--------+
20000018 |00000000| 1FF60000-1FF6FFFF   20000418 |02A80000| 20060000-2006FFFF
         +--------+                              +--------+
2000001C |00000000| 1FF70000-1FF7FFFF   2000041C |00000000| 20070000-2007FFFF
         +--------+                              +--------+
20000020 |00000001| 1FF80000-1FF8FFFF   20000420 |00000000| 20080000-2008FFFF
         +--------+                              +--------+
         ::::::::::                              ::::::::::
         +--------+
20000040 |000000F0| 20000000-2000FFFF
         +--------+
20000044 |00000000| 20010000-2001FFFF
         +--------+
20000048 |00000000| 20020000-2002FFFF
         +--------+
         ::::::::::
    Figure 8. Sample Page Tables
    The task table shows a 4KB read-only area starting at x'1FF80000' and an 8KB read/write area starting at x'20002000'.

    The Master0 table shows a 16KB read-only area starting at x'20053000' and a 16KB write-only area starting at x'20069000'. Remember, task tables begin with x'1FF00000' and local masters start with x'20000000'. The rest of the entries cover to the top of installed memory. Local bus memory is not protected by these tables.

    6.3 Page Table Entry Caching

    In order to limit the number of memory references that the hardware must make to check a page table entry, three separate caches are maintained in the Brighton chip. An 8 entry full-way associative cache is maintained for task page entries. This can cover a total of 512KB in 64KB pieces. If the cache is full and another entry needs to be cached, Brighton will discard the least-recently-used entry to make room for the new one. A 1 entry cache is maintained for Master1 device accesses. A 2 entry cache is maintained for the Master 0 interface. For the Master 0 interface one entry is cached for "writes", and one is cached for "reads", however, accesses are checked against BOTH entries.

    This write causes all task page access bytes presently in the cache to be invalidated. Similarly, a write to the AM_PTBR invalidates its page access byte and a write to the MC_PTBR invalidates the Master 0 slave page access byte cache. Brighton does not check writes to memory to determine if they are cache entries. In order to be sure a change to the tables will be seen by Brighton, the PTBR must be written after the change.

    6.4 How It Works

    1. Brighton determines the accessing unit (80960 task, Master1 or Master0).

    2. Brighton checks if protection is ON for the accessing unit AND the address it is accessing (access address). If it is not then no violation occurs.

    3. Brighton checks if a page table entry has been cached for this address (see 6.3 , "Page Table Entry Caching"). If it has then go to .

    4. Brighton uses the appropriate PTBR (the upper 16 bits of the access address are used as an index) to fetch the correct page table entry.

      Note: This entry will now be cached.

    5. Brighton determines whether this access is a violation or not and takes the appropriate action.

    6.5 Usage Notes for Memory Protection

    7.0 Brighton Timers

    The Brighton module provides timer support through its integrated timer subsystem. Five hardware interval timers are provided (TMR0-4). Four of the timers (TMR0,1,2,4) have a 1ms interval and have 16-bit resolution to allow for timing events from 1ms to 65 seconds. One of the timers (TMR3) is a 24-bit timer that uses a 333ns (actually 1/3 micro second) timing interval to allow for timing events from 333ns to 6 seconds. Each timer's function can be set up by programming the timer control register (see 2.1 , "Timer Control Register (TCR0-4)") and by issuing timer specific commands.

    7.1 Timer Interrupts

    Description
    Each of the five timers can generate an interrupt to the 80960 when a zero count has been reached. Each of the timers interrupt with a separate fixed encoded interrupt.

    Timer # Vector # Suggested Usage
    0 0000 watchdog
    1 1010 software
    2 1011 time of day
    3 1101 performance
    4 1110 time slice
    Table 13. Timer Interrupt Vector Assignment

    8.0 Brighton Serial Debug Port

    The Brighton module provides a fixed function UART built into the chip to eliminate the need for a chip of this type during adapter code debug. This is not intended to be used in an operational system environment, but rather only as a tool in a lab environment during the debug phase of code development. The features of this port are described below.

    The receiver and transmitter can be separately disabled and enabled, or the two can be tied together in a 'wrap' mode for test, as described in 2.7 , "Port Configuration Register (PCR)". The receiver and transmitter data and status registers are described in 2.6 , "Receiver Buffer Port (RxBUF)" and 2.5 , "Transmitter Buffer Port (TxBUF)".

    8.1 Serial Debug Port Interrupts

    The serial debug port has two fixed value interrupts assigned to it. An interrupt is generated when a receiver byte has been accumulated and is available to be read. This interrupt will remain pending as long as there is more data available to be read. Also, an interrupt is generated when the transmitter FIFO is empty.

    The status of the interrupt for the receiver or transmitter can be read in the registers in 2.6 , "Receiver Buffer Port (RxBUF)" and 2.5 , "Transmitter Buffer Port (TxBUF)". The interrupts are cleared when these status registers are read.

    Vector # Function
    0111 Rx byte available
    1000 Tx FIFO empty
    Table 14. Debug Port Interrupt Vector Assignment

    These interrupts can be enabled or disabled as described in 2.7 , "Port Configuration Register (PCR)".

    9.0 Interrupt Function

    The following interrupts may be generated by Brighton:

    BRINT3:0 Description Clearing Register
    0000 Timer 0 (highest priority -- ideal for watchdog) see TCR, page 2.1 , "Timer Control Register (TCR0-4)"
    0001 Multi-Bit ECC Error access by processor see ECCSTAT, page 2.21 , "ECC Status Register (ECCSTAT)"
    0010 Local Bus Exception with Brighton Master see LEXSTAT, page 2.17 , "Local Bus Exception Status Register (LEXSTAT)"
    0011 Local Bus Parity with Brighton Master see LEXSTAT, page 2.17 , "Local Bus Exception Status Register (LEXSTAT)"
    0100 Protection (caused by a task memory protection violation) see TPSTAT, page 2.13 , "Task Protection Status Register (TPSTAT)"
    0101 Master0 protection error see LPATR, page 2.14 , "Local Bus Protection Address Trap Register (LPATR)"
    0110 Master1 protection error see LPATR, page 2.14 , "Local Bus Protection Address Trap Register (LPATR)"
    0111 Serial port data received see RXBUF, page 2.6 , "Receiver Buffer Port (RxBUF)"
    1000 Serial port Tx FIFO empty see TXBUF, page 2.5 , "Transmitter Buffer Port (TxBUF)"
    1001 Reserved
    1010 Timer 1 see TCR, page 2.1 , "Timer Control Register (TCR0-4)"
    1011 Timer 2 see TCR, page 2.1 , "Timer Control Register (TCR0-4)"
    1100 Timer 3 see TCR, page 2.1 , "Timer Control Register (TCR0-4)"
    1101 Timer 4 see TCR, page 2.1 , "Timer Control Register (TCR0-4)"
    1110 Multiple Single-Bit ECC Errors Detected Interrupt (lowest priority) see SBECCR, page 2.19 , "Single-Bit ECC Error Register (SBECCR)"
    Table 15. Brighton Interrupts

    These are listed from highest priority to lowest (internal to Brighton). A simple priority encoder is used to output the highest pending interrupt. The output will remain until the interrupt is cleared or a higher interrupt is generated. These outputs are synchronized with the clock.

    9.1 Manufacturing Test

    9.1.1 Driver Inhibit

    To allow for testing of other modules connected to Brighton, all of Brighton's drivers can be tri-stated as follows:

    9.2 Testing Brighton Connections

    Testing whether or not Brighton is correctly soldered to the card is divided in three parts.

    9.2.1 Part 1

    Part 1 tests a majority of the signals. This part is enabled when: This test takes a group of input signals through a NAND tree with the output of the tree appearing on an output pin. 
          +-----+
IN1 --+ INV |O--+   +-----+
      +-----+   +---+     |
                    |NAND |O-+  +-----+
IN2 ----------------+     |  +--+     |
                    +-----+     |NAND |O---+
IN3 ----------------------------+     |    |
                                +-----+    |
                                           |      +-----+
                                           +------+     |
                                                  |NAND |O-----------OUT
INn ----------------------------------------------+     |
                                                  +-----+
                             NAND TREE
    The test begins with all the inputs set to '1'. Then, starting with IN1 (then IN2, IN3...INn) they are changed to '0' (they are not changed back to '1'). Each time a signal is changed the output should toggle.

    Listed in Table 16. are the input and output signals for the seven NAND trees in Brighton. Also, the state the output is in when all its corresponding inputs are '1's.

    OUTPUT SIGNAL ALL 1'S INPUTS (listed in order starting with IN1)
    -IW 0 P_D(20:31), P_W/-R, -POR, -P_BLAST, -P_DMA, -P_BE(0:3), P_ADS, P_A(24:31)
    -DW 1 PCLK, C_CLK, P_D(0:19)
    TXDATA 1 ID(2:31)
    BRINT0_ 0 L_AD(24:31), L_ADP(0:3), L_BE(0:3), ICB(0:6), ID(0:1)
    BRINT1_ 1 L_AD(0:23)
    BRINT2_ 0 DD(26:31), DCB(0:6), RXDATA, L_WR, -LEXCPT, -L_READY, -L_BLAST, -L_ADS, -L_GRANT2_, -L_GRANT1_, -L_GRANT0_, -BRIREQ_, -L_REQ0, -L_REQ1, -L_REQ2, -BRIGNT
    BRINT3_ 1 DD(0:25)
    Table 16. NAND tree inputs/outputs

    9.2.2 Part 2

    Part 2 tests the RASs, CASs, -PREADY and -ROSCS. It uses the scan chains in Brighton in a flush-thru mode to toggle these signals. To enable the mode make sure: Table 17. shows which inputs toggle which outputs.

    INPUT SIGNAL OUTPUTS OF SAME POLARITY AS INPUT OUTPUTS OF OPPOSITE POLARITY AS INPUT
    P_W/-R -IRAS1 -ROSCS, -P_READY
    -P_BE2 -ICAS0, -ICAS1 -IRAS0
    PA(5) (none) -DRAS1
    PA(2) (none) -DRAS0, -DCAS0, -DCAS1
    Table 17. Scan-chain flush-thru signal correspondence

    9.2.3 Part 3

    The setup for part 3 is a bit more complicated. The vectors that should be applied to Brighton to setup this test are shown in Table 18.. -DI should be HIGH during the entire test. Also, note that the first vector is easily attained from part 2.

    VECTOR # A_CLK B_CLK C_CLK POR PCLK -MTEST P_W/-R -P_BE2 P_A(5) P_A(2)
    1 L H L X H H L H L L
    2 H L L X H H L H L L
    3 H L H L L L X X X X
    4 H L L L L L X X X X
    5 H H L L H L X X X X
    H = HIGH, L = LOW, X = DON'T CARE
    Table 18. Vectors for Manufacturing Test Part 3
    After applying these five vectors the tester can now toggle certain P_A inputs and observe a corresponding change on the DA or IA outputs. The exact correlation is shown in Table 19..

    INPUT OUTPUT
    P_A(2) IA(0)
    P_A(3) IA(1)
    P_A(4) IA(2)
    P_A(5) IA(3)
    P_A(6) IA(4)
    P_A(7) IA(5)
    P_A(8) IA(6)
    P_A(9) IA(7)
    P_A(10) IA(8)
    P_A(20) IA(9)
    P_A(23) IA(10),DA(11)
    P_A(24) IA(11)
    P_A(11) DA(0)
    P_A(12) DA(1)
    P_A(13) DA(2)
    P_A(14) DA(3)
    P_A(15) DA(4)
    P_A(16) DA(5)
    P_A(17) DA(6)
    P_A(18) DA(7)
    P_A(19) DA(8)
    P_A(21) DA(9)
    P_A(22) DA(10)
    Table 19. PA to IA and DA bit correlation

    10.0 Brighton Timings

    10.1 Brighton CFE Timings

    This section documents the CFE local bus timings. All local bus signal timings (outputs) are based on a capacitance of 55pf except -L_GNT (30 pf) and -BRIREQ (20 pf). The MAX timings can be approximated for lower capacitances (down to 30pf) by subtracting 0.25ns per pf. (e.g. at 35pf subtract (55pf-35pf)*.25ns/pf = 5 ns from max timing.) All timings are referenced to the rising edge of the PCLK.

    Table 20. Brighton CFE local bus timings, outputs
    Symbol Description Min (ns) Max (ns) Notes
    Tov, Toh -L_ADS 8 29
    Tov, Toh L_AD, L_ADP (address) 8 22
    Tov, Toh -L_BLAST 7 20
    Tov, Toh -L_BE, L_W/-R 8 22 1
    Tov, Toh L_AD, L_ADP (data from memory) 11 19 2
    Tov, Toh L_AD, L_ADP (data from Brighton register or master write) 8 29
    Tov, Toh -L_EXCPT 9 29
    Tov, Toh -L_READY 7 20
    Tov, Toh -L_GNT 9 28
    Tov, Toh -BRIREQ 8 25

    Notes:

    1. The CFE spec shows these signals as valid only during the address state, however, Brighton (as a master) holds these through BLAST.
    2. This timing is based on capacitances and memory speed shown in 10.3 , "Memory Timing".

    Table 21. Brighton CFE local bus timings, inputs
    Symbol Description Min Tis (ns) Min Tih (ns) Notes
    Tis, Tih -L_ADS, -L_BLAST, -L_BE, L_W/-R, -L_READY, -L_EXCPT, -L_REQ, -BRIGNT 7 6
    Tis, Tih L_AD, L_ADP (address) 10 6
    Tis, Tih L_AD, L_ADP (data) 44 6 1

    Notes:

    1. This timing is based on capacitances and memory speed shown in 10.3 , "Memory Timing". The setup time appears large because the data must be setup based on zero wait state timings. 


             +----+    +---  \     +----+
PCLK     |    |    |     /     |    |
         +    +----+     \  ---+    +----
                         /
         ++++----------  \  ------+++++++
outputs  ++++      |     /     |  +++++++
         ++++----------  \  ------+++++++
        >|  |<-Tov       /    >|  |<-Toh
                         \
         ++++----------  /  ------+++++++
inputs   ++++      |     \     |  +++++++
         ++++----------  /  ------+++++++
           >|      |<-Tis     >|  |<-Tih
    Figure 9. Brighton input and output timing reference 
             +----+    +----+    +----+    +----+    +---- /    +----+    +----+    +----+    +----+
PCLK     |    |    |    |    |    |    |    |    |     \    |    |    |    |    |    |    |    |
         +    +----+    +----+    +----+    +----+     / ---+    +----+    +----+    +----+    +----
         |         |         |         |         |     \    |         |         |         |
         --+       | +-------------------------------- / -----+       | +---------------------------
-L_ADS   | |       | |       |         |         |     \    | |       | |       |         |
         | +---------+       |         |         |     /    | +---------+       |         |
         |         |         |         |         |     \    |         |         |         |
         +++---------++++++------------------------+++ / ++++++---------+++++++++++++-------++++++++
L_AD     +++       | ++++++  |         |         | +++ \ ++++++       | +++++++++++++     | ++++++++
L_ADP    +++---------++++++------------------------+++ / ++++++---------+++++++++++++-------++++++++
         |         |         |         |         |     \    |         |         |         |
         +++---------------------------------------+++ / ++++++       |         |         | ++++++++
L_W/-R   +++       |         |         |         | +++ \ ++++++       |         |         | ++++++++
         +++       |         |         |         | +++ / ++++++-----------------------------++++++++
         |         |         |         |         |     \    |         |         |         |
         +++---------------------------------------+++ / ++++++-----------------------------++++++++
-L_BE    +++       |         |         |         | +++ \ ++++++       |         |         | ++++++++
         +++---------------------------------------+++ / ++++++-----------------------------++++++++
         |         |         |         |         |     \    |         |         |         |
         --------------------------------+       | +-- / -------------------------+       | +-------
-L_READY |         |         |         | |       | |   \    |         |         | |       | |
         |         |         |         | +---------+   /    |         |         | +---------+
         |         |         |         |         |     \    |         |         |         |
         ----------------------+       |         | +-- / -------------------------+       | +-------
-L_BLAST |         |         | |       |         | |   \    |         |         | |       | |
         |         |         | +-------------------+   /    |         |         | +---------+
    Figure 10. Brighton local bus master timing

    A two (one is minimum) wait-state write and one wait-state read are shown. 

             +----+    +----+    +----+    +----+    +----+    +----+    +----+    +----+    +----+    +----+
PCLK     |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         +    +----+    +----+    +----+    +----+    +----+    +----+    +----+    +----+    +----+    +----
         |         |         |         |         |         |         |         |         |         |
         ---+      |         |         |         |         |         |         | +-------------------+-------
-L_REQ   |  |      |         |         |         |         |         |         | |       |         | |
         |  +--------------------------------------------------------------------+-------------------+-------
         |         |         |         |         |         |         |         |         |         |
         ------------+       |         |         |         |         |         |         |         | +-------
-L_GNT   |         | |       |         |         |         |         |         |         |         | |
         |         | +-------------------------------------------------------------------------------+-------
         |         |         |         |         |         |         |         |         |         |
         ----------------------+       | +-------------------------------------------------------------------
-L_ADS   |         |         | |       | |       |         |         |         |         |         |
         |         |         | +---------+       |         |         |         |         |         |
         |         |         |         |         |         |         |         |         |         |
         +++++++++++++++++++++++---------+++++++++++++++++++++++++++++++---------+++++++++++---------++++++++
L_AD     +++++++++++++++++++++++       | +++++++++++++++++++++++++++++++       | +++++++++++       | ++++++++
L_ADP    +++++++++++++++++++++++---------+++++++++++++++++++++++++++++++---------+++++++++++---------++++++++
         |         |         |         |         |         |         |         |         |         |
         +++++++++++++++++++++++       | ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
L_W/-R   +++++++++++++++++++++++       | ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-L_BE    +++++++++++++++++++++++---------++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
         |         |         |         |         |         |         |         |         |         |
         --------------------------------------------------------------+       | +---------+       | +-------
-L_READY |         |         |         |         |         |         | |       | |       | |       | |
         |         |         |         |         |         |         | +---------+       | +---------+
         |         |         |         |         |         |         |         |         |         |
         ------------------------------------------------------------------------+       |         | +-------
-L_BLAST |         |         |         |         |         |         |         | |       |         | |
         |         |         |         |         |         |         |         | +-------------------+
    Figure 11. Brighton local bus slave read timing

    A minimum wait-state two-word burst read from packet memory is shown. 

             +----+    +----+    +----+    +----+    +----+    +----+    +----+    +----+    +----+
PCLK     |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         +    +----+    +----+    +----+    +----+    +----+    +----+    +----+    +----+    +----
         |         |         |         |         |         |         |         |         |
         ---+      |         |         |         |         |         | +-------------------+-------
-L_REQ   |  |      |         |         |         |         |         | |       |         | |
         |  +----------------------------------------------------------+-------------------+-------
         |         |         |         |         |         |         |         |         |
         ------------+       |         |         |         |         |         |         | +-------
-L_GNT   |         | |       |         |         |         |         |         |         | |
         |         | +---------------------------------------------------------------------+-------
         |         |         |         |         |         |         |         |         |
         ----------------------+       | +---------------------------------------------------------
-L_ADS   |         |         | |       | |       |         |         |         |         |
         |         |         | +---------+       |         |         |         |         |
         |         |         |         |         |         |         |         |         |
         +++++++++++++++++++++++---------+++++++++++++++---------------+++++---------------++++++++
L_AD     +++++++++++++++++++++++       | +++++++++++++++   |         | +++++   |         | ++++++++
L_ADP    +++++++++++++++++++++++---------+++++++++++++++---------------+++++---------------++++++++
         |         |         |         |         |         |         |         |         |
         +++++++++++++++++++++++---------++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
L_W/-R   +++++++++++++++++++++++       | ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
         +++++++++++++++++++++++       | ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
         |         |         |         |         |         |         |         |         |
         +++++++++++++++++++++++       | ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-L_BE    +++++++++++++++++++++++       | ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
         +++++++++++++++++++++++---------++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
         |         |         |         |         |         |         |         |         |
         ----------------------------------------------------+       | +---------+       | +-------
-L_READY |         |         |         |         |         | |       | |       | |       | |
         |         |         |         |         |         | +---------+       | +---------+
         |         |         |         |         |         |         |         |         |
         --------------------------------------------------------------+       |         | +-------
-L_BLAST |         |         |         |         |         |         | |       |         | |
         |         |         |         |         |         |         | +-------------------+
    Figure 12. Brighton local bus slave write timing

    A minimum wait-state two-word burst write to packet memory is shown. 

             +----+    +----+    +----+    +----+    +----+    +----+    |
PCLK     |    |    |    |    |    |    |    |    |    |    |    |    |
         +    +----+    +----+    +----+    +----+    +----+    +----|
         |         |         |         |         |         |         |
         --+       | +-----------------------------------------------|
-L_ADS   | |       | |       |         |         |         |         |
         | +---------+       |         |         |         |         |
         |         |         |         |         |         |         |
         +++---------++++++++++++++++++++++++++++++++--------++++++++|
L_AD     +++       | ++++++++++++++++++++++++++++++++bad data++++++++|
L_ADP    +++---------++++++++++++++++++++++++++++++++--------++++++++|
         |         |         |         |         |         |         |
         +++       | ++++++++++++++++++++++++++++++++++++++++++++++++|
L_W/-R   +++       | ++++++++++++++++++++++++++++++++++++++++++++++++|
         +++---------++++++++++++++++++++++++++++++++++++++++++++++++|
         |         |         |         |         |         |         |
         +++---------++++++++++++++++++++++++++++++++++++++++++++++++|
-L_BE    +++       | ++++++++++++++++++++++++++++++++++++++++++++++++|
         +++---------++++++++++++++++++++++++++++++++++++++++++++++++|
         |         |         |         |         |         |         |
         ------------------------------------------+       | +-------|
-L_READY |         |         |         |         | |       | |       |
         |         |         |         |         | +---------+       |
         |         |         |         |         |         |         |
         ----------------------------------------------------+       |         | ,-------
-L_EXCPT |         |         |         |         |         | |       |         | |
         |         |         |         |         |         | +-------------+
    Notes:

    1. An exception caused by an ECC error can also occur on a sub-word
      write to memory. The timing looks similar except -L_READY would not
      be driven.

    2. An exception caused by bad data parity would have the same timing as above.
    Figure 13. Exception caused by multi-bit ECC error (memory read)

    A three (minimum) wait-state read from packet memory is shown.

    10.2 Brighton Processor Interface Timings

    This section documents the Processor interface timings. Signal timings (outputs) are based on the following capacitances:

    Table 22. Capacitance values used for timings
    Signal Description Min (pf) Max (pf)
    P_D 20 40
    -P_READY 20 25
    -ROSCS 20 25
    INT 20 30
    The MAX timings can be approximated for different capacitances (20 to 50pf) by adding 0.25ns per pf. (e.g. -P_READY with 50 pf, add (50pf - 25pf)*.25ns/pf = 6.25ns to max timing.) All timings are referenced to the rising edge of the PCLK.

    See Figure 9. for definition of Tov and Toh.

    Table 23. Processor interface timings, outputs
    Symbol Description Min Max Notes
    Tov, Toh P_D (from memory) 8 18 1
    Tov, Toh P_D (from local bus or Brighton register) 8 30
    Tov, Toh -P_READY 8 22
    Tov, Toh -ROSCS 7 21
    Tov, Toh INT 9 27

    Notes:

    1. This timing is based on capacitances and memory speed shown in 10.3 , "Memory Timing".

    Table 24. Processor interface timings, inputs
    Symbol Description Min Tis Min Tih Notes
    Timings for inputs are as listed in the 80960CA data sheet contained in Intel's 1992 Multimedia and Supercomputing Processors. 

             +----+    +----+    +----+    +----+    +----+    +----+    +----+    +----+
PCLK     |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         +    +----+    +----+    +----+    +----+    +----+    +----+    +----+    +----
         |         |         |         |         |         |         |         |
         --+       | +-------------------------------------------------------------------
-P_ADS   | |       | |       |         |         |         |         |         |
         | +---------+       |         |         |         |         |         |
         |         |         |         |         |         |         |         |
         +++---------------------------------------------------++------------------++++++
P_A      +++       |         |         |         |         |   ++    |         |   ++++++
         +++---------------------------------------------------++------------------++++++
         |         |         |         |         |         |         |         |
         +++++++++++++++++++++++++++++++++++++++++++---------+++++++++++---------++++++++
P_D      +++++++++++++++++++++++++++++++++++++++++++       | +++++++++++       | ++++++++
         +++++++++++++++++++++++++++++++++++++++++++---------+++++++++++---------++++++++
         |         |         |         |         |         |         |         |
         +++       |         |         |         |         |         |         | ++++++++
P_W/-R   +++       |         |         |         |         |         |         | ++++++++
-P_BE    +++---------------------------------------------------------------------++++++++
         |         |         |         |         |         |         |         |
         ------------------------------------------+       | +---------+       | +-------
-P_READY |         |         |         |         | |       | |       | |       | |
         |         |         |         |         | +---------+       | +---------+
         |         |         |         |         |         |         |         |
         ----------------------------------------------------+       |         | +-------
-P_BLAST |         |         |         |         |         | |       |         | |
         |         |         |         |         |         | +-------------------+
    Figure 14. Processor read of memory

    A minimum wait-state two-word burst read from memory is shown. 

             +----+    +----+    +----+    +----+    +----+    +----+    +----+
PCLK     |    |    |    |    |    |    |    |    |    |    |    |    |    |
         +    +----+    +----+    +----+    +----+    +----+    +----+    +----
         |         |         |         |         |         |         |
         --+       | +---------------------------------------------------------
-P_ADS   | |       | |       |         |         |         |         |
         | +---------+       |         |         |         |         |
         |         |         |         |         |         |         |
         +++-----------------------------------------++------------------++++++
P_A      +++       |         |         |         |   ++    |         |   ++++++
         +++-----------------------------------------++------------------++++++
         |         |         |         |         |         |         |
         +++++++++++++++++++++++++++++++++---------+++++++++++---------++++++++
P_D      +++++++++++++++++++++++++++++++++       | +++++++++++       | ++++++++
         +++++++++++++++++++++++++++++++++---------+++++++++++---------++++++++
         |         |         |         |         |         |         |
         +++-----------------------------------------------------------++++++++
P_W/-R   +++       |         |         |         |         |         | ++++++++
         +++       |         |         |         |         |         | ++++++++
         |         |         |         |         |         |         |
         +++       |         |         |         |         |         | ++++++++
-P_BE    +++       |         |         |         |         |         | ++++++++
         +++-----------------------------------------------------------++++++++
         |         |         |         |         |         |         |
         --------------------------------+       | +---------+       | +-------
-P_READY |         |         |         | |       | |       | |       | |
         |         |         |         | +---------+       | +---------+
         |         |         |         |         |         |         |
         ------------------------------------------+       |         | +-------
-P_BLAST |         |         |         |         | |       |         | |
         |         |         |         |         | +-------------------+
    Figure 15. Processor write to memory

    A minimum wait-state two-word burst write to memory is shown. 

             +----+    +----+    +--- /     +----+    +----+    +----+
PCLK     |    |    |    |    |    \     |    |    |    |    |    |
         +    +----+    +----+    / ----+    +----+    +----+    +----
         |         |         |    \     |         |         |
         --+       | +----------- / ----------------------------------
-P_ADS   | |       | |       |    \     |         |         |
         | +---------+       |    /     |         |         |
         |         |         |    \     |         |         |
         ------------------------ / ----------------------------------
-P_READY |         |         |    \     |         |         |
         |         |         |    /     |         |         |
         |         |         |    \     |         |         |
         ------------------------ / ------+       | +-----------------
-P_BLAST |         |         |    \     | |       | |       |
         |         |         |    /     | +---------+       |
         |         |         |    \     |         |         |
         -------------+      |    /     |         |         |  +------
-ROSCS   |         |  |      |    \     |         |         |  |
         |         |  +---------- / ---------------------------+
    Figure 16. ROSCS timing

    -ROSCS goes active the state after ADS and inactive the state after BLAST goes high.

    10.3 Memory Timing

    This section lists several timings associated with the memory controller portion of Brighton. Please take the following into consideration when viewing these:

    10.3.1 Abbreviations/Symbols

    The following abbreviations/symbols are used in this section:

    Dmem
    Data (packet) memory

    Imem
    Instruction memory

    ^
    Rising edge of PCLK

    %
    Falling edge of PCLK

    Table 27. Memory Related Timings
    Symbol Description Min (ns) Max (ns) Notes
    T1a 80960CA address to Dmem row address 8 27 1
    T1a CFE address to Dmem row address 5 28 1
    T1a 80960CA address to Imem row address 7 26 1
    T1a CFE address to Imem row address - - 2
    T1b ^ to Dmem row address 12 39 3
    T1b ^ to Imem row address 11 42 3
    T2 Dmem data to 80960CA data 11 28 4
    T2 Dmem data to CFE data 12 27 4
    T2 Dmem data to CFE data parity 12 32 4
    T2 Imem data to 80960CA data 11 24 4
    T2 Imem data to CFE data 11 27 4
    T2 Imem data to CFE data parity 11 32 4
    T3 80960CA data to Dmem data 6 26
    T3 CFE bus data to Dmem data 6 26
    T3 80960CA data to Imem data 5 25
    T3 CFE bus data to Imem data 4 25
    T4 % to 1st Dmem column address 9 31
    T4 % to 1st Imem column address 9 34
    T4 % to 2nd (or subsequent) Dmem column address 14 39
    T4 % to 2nd (or subsequent) Imem column address 13 36
    T5 ^ to Dmem RAS low 8 21
    T5 ^ to Dmem RAS high 7 22
    T5 ^ to Imem RAS low 8 20
    T5 ^ to Imem RAS high 7 21
    T6 ^ to Dmem CAS low 11 27
    T6 ^ to Dmem CAS high 9 28
    T6 ^ to Imem CAS low 10 27
    T6 ^ to Imem CAS high 8 28
    T7 % to Dmem CAS low 9 21
    T7 % to Dmem CAS high 7 22
    T7 % to Imem CAS low 9 21
    T7 % to Imem CAS high 7 22
    T8 ^ to Dmem WE low 13 34
    T8 ^ to Dmem WE high 10 34
    T8 ^ to Imem WE low 13 35
    T8 ^ to Imem WE high 9 34

    Notes:

    1. This timing is valid only when the memory owner was the default owner (see 5.0 , "Arbiter Function"), otherwise T1b applies.
    2. The CFE bus is never the default bus to Imem so there is no flow-thru address timing.
    3. This timing is valid for all 'non-default' owner accesses (ignore the shown ADS timing).
    4. Min timing is from ^. 

    
pclk                +----+    +----+    +----+    +----+    +----+    +----+    +----+    +----+
                    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
                    +    +----+    +----+    +----+    +----+    +----+    +----+    +----+    +----
                    |         |    |    |    |         |         |         |    |
ads                 --+       | +-------------------------------------------------------------------
                    | |       | |  |    |    |         |         |         |    |
                    | +---------+  |    |    |         |         |         |    |
                    |         | |  |    |    |         |         |         |    |
ready               -------------------------------------------+ |       +---------+         +------
                    |         | |  |    |    |         |       | |       | |    |  |         |
                    |         | |  |    |    |         |       +---------+ |    |  +---------+
                    |         | |  |    |    |         |         |         |    |
blast               ----------------------------------------------------+  |    |           +-------
                    |         | |  |    |    |         |         |      |  |    |           |
                    |         | |  |    |    |         |         |      +-------------------+
                    |         | |  |    |    |         |         |         |    |
cfe a/d bus         +++++++----++++++++++++++++++++++++++++++++++------++++++++++++++------+++++++++
80960 addr bus      +++++++addr++++++++++++++++++++++++++++++++++  D1  ++++++++++++++  D2  +++++++++
80960 data bus      +++++++----++++++++++++++++++++++++++++++++++------++++++++++++++------+++++++++
                    |     +T1a->|  |    |    |         |        ||         |    |
                    +----T1b--->|  +T4->|    |         +T4->|   ||         |    |
                    |         | |  |    |    |         |        ||         |    |
                    +++++++++++++------++------------------++------------------+++++++++++++++++++++
dram_addr           +++++++++++++ row  ++    col addr 1    ++    col addr 2    +++++++++++++++++++++
                    +++++++++++++------++------------------++------------------+++++++++++++++++++++
                    |         +T5->|    |    |         |        ||         |    +T5->|
                    |         |    |    |    |         |        ||         |    |
                    ---------------+    |    |         |        ||         |    |    +--------------
ras                 |         |    |    |    |         |        ||         |    |    |
                    |         |    +-------------------------------------------------+
                    |         |    |    +-T6->|        +T7>|    |+T7>|     +T7>||
                    |         |    |    |    ||        |   |    ||         |   ||
                    --------------------------+        |   +---------+     |   +--------------------
cas                 |         |    |    |    ||        |   |    ||   |     |   ||
                    |         |    |    |    |+------------+    ||   +---------+|
                    |         |    |    |    |         |---T2---+|         |    |
                    |         |    |    |    |         |         |         |    |
                    ++++++++++++++++++++++++++++++++++++----++++++++++++++++----++++++++++++++++++++
dram_data           ++++++++++++++++++++++++++++++++++++ D1 ++++++++++++++++ D2 ++++++++++++++++++++
                    ++++++++++++++++++++++++++++++++++++----++++++++++++++++----++++++++++++++++++++
    Figure 17. Memory read timing 
    
pclk                +----+    +----+    +----+    +----+    +----+    +----+    +----+    +-
                    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
                    +    +----+    +----+    +----+    +----+    +----+    +----+    +----+
                    |         |    |    |         |    |    |         |         |
ads                 --+       | +-----------------------------------------------------------
                    | |       | |  |    |         |    |    |         |         |
                    | +---------+  |    |         |    |    |         |         |
                    |         |    |    |         |    |    |         |         |
ready               ---------------------------------+ |    |  +---------+      |  +--------
                    |         |    |    |         |  | |    |  |      |  |      |  |
                    |         |    |    |         |  +---------+      |  +---------+
                    |         |    |    |         |    |    |         |         |
blast               -------------------------------------------+      |         |  +--------
                    |         |    |    |         |    |    |  |      |         |  |
                    |         |    |    |         |    |    |  +-------------------+
                    |         |    |    |         |    |    |         |         |
cfe a/d bus         +++++++----+++++++-----------------------++------------------+++++++++++
80960 addr bus      +++++++addr+++++++        D1             ++        D2        +++++++++++
80960 data bus      +++++++----+++++++-----------------------++------------------+++++++++++
                    |     +T1a->|  | |  |         |    |    | |       |         |
                    +----T1b--->|  +T4->|         |    +T4->| |       |         |
                    |         | |  | |  |         |    |    | |       |         |
                    +++++++++++++------++------------------++------------------+++++++++++++
dram_addr           +++++++++++++ row  ++    col addr 1    ++    col addr 2    +++++++++++++
                    +++++++++++++------++------------------++------------------+++++++++++++
                    |         +T5->| |  |         |    |    | |       |         +T5->|
                    |         |    | |  |         |    |    | |       |         |    |
                    ---------------+ |  |         |    |    | |       |         |    +------
ras                 |         |    | |  |         |    |    | |       |         |    |
                    |         |    +-------------------------------------------------+
                    |         |    | |  |         +-T6->|   +-T6->|   +-T6->|   +-T6->|
                    |         |    | |  |         |    ||   | |   |   |     |   |     |
                    ------------------------------------+   | |   +---------+   |     +-----
cas                 |         |    | |  |         |    ||   | |   |   |     |   |     |
                    |         |    | |  |         |    |+---------+   |     +---------+
                    |         |    | |  +-T8-->|  |    |    | |       |         +-T8-->|
                    |         |    | |  |      |  |    |    | |       |         |      |
                    ---------------------------+  |    |    | |       |         |      +----
we                  |         |    | |  |      |  |    |    | |       |         |      |
                    |         |    | |  |      +---------------------------------------+
                    |         |    | +---T3-->|   |    |    | +---T3-->|        |
                    |         |    |    |     |   |    |    |         ||        |
                    +++++++++++++++++++++++++++---------------------++++----------------++++
dram_data           +++++++++++++++++++++++++++         D1          ++++       D2       ++++
                    +++++++++++++++++++++++++++---------------------++++----------------++++

    
pclk                +----+    +----+    +----+    +----+    +----+    +----+    +----+
                    |    |    |    |    |    |    |    |    |    |    |    |    |    |
                    +    +----+    +----+    +----+    +----+    +----+    +----+    +----
                    |         |    |    |              |    |         |         |
                    |         |    |    |              |    |         |         |
ads                 --+       | +---------------------------------------------------------
                    | |       | |  |    |              |    |         |         |
                    | +---------+  |    |              |    |         |         |
                    |         |    |    |              |    |         |         |
ready               -----------------------------------------------------+      |  +------
                    |         |    |    |              |    |         |  |      |  |
                    |         |    |    |              |    |         |  +---------+
                    |         |    |    |              |    |         |         |
blast               ------------+  |    |              |    |         |         |  +------
                    |         | |  |    |              |    |         |         |  |
                    |         | +--------------------------------------------------+
                    |         |    |    |              |    |         |         |
cfe a/d bus         +++++++----++------------------------------------------------+++++++++
80960 addr bus      +++++++addr++             data                               +++++++++
80960 data bus      +++++++----++------------------------------------------------+++++++++
                    |     +T1a->|  |    |              |    |         |         |
                    +----T1b--->|  +T4->|              |    |         |         |
                    |         | |  |    |              |    |         |         |
                    +++++++++++++------++--------------------------------------+++++++++++
dram_addr           +++++++++++++ row  ++               col addr               +++++++++++
                    +++++++++++++------++--------------------------------------+++++++++++
                    |         +T5->|    |              |    |         |         +T5->|
                    |         |    |    |              |    |         |         |    |
ras                 ---------------+    |              |    |         |         |    +----
                    |         |    |    |              |    |         |         |    |
                    |         |    +-------------------------------------------------+
                    |         |    |    +-T6->|        +T7>||         +-T6->|   +-T6->|
                    |         |    |    |     |        |   ||         |     |   |     |
                    --------------------------+        |   +----------------+   |     +---
cas                 |         |    |    |     |        |   ||         |     |   |     |
                    |         |    |    |     +------------+|         |     +---------+
                    |         |    |    |              |    +-T8-->|  |         +-T8-->|
                    |         |    |    |              |    |      |  |         |      |
                    -----------------------------------------------+  |         |      +--
we                  |         |    |    |              |    |      |  |         |      |
                    |         |    |    |              |    |      +-------------------+
                    |         |    |    |              |    |         |         |
                    ++++++++++++++++++++++++++++++++++++---------++++++-----------------++
dram_data           ++++++++++++++++++++++++++++++++++++read data++++++  modified data  ++
                    ++++++++++++++++++++++++++++++++++++---------++++++-----------------++
    Figure 19. Memory read-modify-write timing

    Appendix A. Brighton Pin Name/Number cross reference

    11.1 Brighton Pin Names/Numbers (listed by pin name)

    Name        #
---------  ---
A_CLK0     013
BRGNT_     007
BRINT0_    300
BRINT1_    301
BRINT2_    302
BRINT3_    303
BRREQ_     006
B_CLK0     014
COMP       075
C_CLK0     192
DA(00)     243
DA(01)     244
DA(02)     245
DA(03)     246
DA(04)     247
DA(05)     250
DA(06)     251
DA(07)     261
DA(08)     263
DA(09)     264
DA(10)     273
DA(11)     276
DCAS0_     270
DCAS1_     274
DCB(00)    237
DCB(01)    242
DCB(02)    255
DCB(03)    260
DCB(04)    269
DCB(05)    281
DCB(06)    287
DD(00)     233
DD(01)     235
DD(02)     236
DD(03)     239
DD(04)     240
DD(05)     241
DD(06)     252
DD(07)     253
DD(08)     254
DD(09)     256
DD(10)     258
DD(11)     259
DD(12)     262
DD(13)     265
DD(14)     268
DD(15)     271
DD(16)     278
DD(17)     280
DD(18)     282
DD(19)     283
DD(20)     286
DD(21)     288
DD(22)     289
DD(23)     290
DD(24)     291
DD(25)     293
DD(26)     294
DD(27)     295
DD(28)     296
DD(29)     297
DD(30)     298
DD(31)     299
DI_IN_     078
DRAS0_     272
DRAS1_     277
DW_        279
GND        012
GND        020
GND        031
GND        039
GND        046
GND        052
GND        060
GND        066
GND        076
GND        084
GND        090
GND        096
GND        103
GND        109
GND        115
GND        121
GND        129
GND        139
GND        152
GND        161
GND        167
GND        172
GND        179
GND        185
GND        191
GND        193
GND        198
GND        214
GND        228
GND        238
GND        248
GND        257
GND        267
GND        275
GND        284
GND        292
GND        304
IA(00)     144
IA(01)     143
IA(02)     142
IA(03)     141
IA(04)     140
IA(05)     138
IA(06)     137
IA(07)     136
IA(08)     135
IA(09)     134
IA(10)     132
IA(11)     130
ICAS0_     128
ICAS1_     124
ICB(00)    120
ICB(01)    116
ICB(02)    110
ICB(03)    105
ICB(04)    100
ICB(05)    094
ICB(06)    089
ID(00)     125
ID(01)     123
ID(02)     122
ID(03)     119
ID(04)     118
ID(05)     117
ID(06)     113
ID(07)     112
ID(08)     111
ID(09)     108
ID(10)     107
ID(11)     106
ID(12)     104
ID(13)     102
ID(14)     101
ID(15)     099
ID(16)     098
ID(17)     095
ID(18)     093
ID(19)     092
ID(20)     091
ID(21)     088
ID(22)     087
ID(23)     086
ID(24)     085
ID(25)     083
ID(26)     082
ID(27)     081
ID(28)     080
ID(29)     079
ID(30)     074
ID(31)     073
IRAS0_     131
IRAS1_     126
IW_        127
LAD(00)    025
LAD(01)    026
LAD(02)    027
LAD(03)    028
LAD(04)    029
LAD(05)    030
LAD(06)    032
LAD(07)    033
LAD(08)    034
LAD(09)    035
LAD(10)    036
LAD(11)    037
LAD(12)    040
LAD(13)    041
LAD(14)    042
LAD(15)    043
LAD(16)    044
LAD(17)    045
LAD(18)    047
LAD(19)    048
LAD(20)    049
LAD(21)    050
LAD(22)    051
LAD(23)    053
LAD(24)    054
LAD(25)    055
LAD(26)    056
LAD(27)    058
LAD(28)    059
LAD(29)    061
LAD(30)    062
LAD(31)    063
LADP0      064
LADP1      065
LADP2      067
LADP3      068
LADS_      023
LBE0_      069
LBE1_      070
LBE2_      071
LBE3_      072
LBLAST_    019
LEXCPT_    008
LGNT0_     009
LGNT1_     010
LGNT2_     011
LREADY_    022
LREQ0_     015
LREQ1_     016
LREQ2_     017
LW_R_      018
MTST_      005
PADS_      155
PBE0_      149
PBE1_      148
PBE2_      147
PBE3_      146
PBLAST_    150
PCLK1      024
PD(00)     197
PD(01)     196
PD(02)     195
PD(03)     194
PD(04)     189
PD(05)     188
PD(06)     187
PD(07)     186
PD(08)     184
PD(09)     183
PD(10)     182
PD(11)     181
PD(12)     180
PD(13)     178
PD(14)     177
PD(15)     176
PD(16)     175
PD(17)     174
PD(18)     171
PD(19)     170
PD(20)     169
PD(21)     168
PD(22)     166
PD(23)     165
PD(24)     164
PD(25)     163
PD(26)     162
PD(27)     160
PD(28)     159
PD(29)     158
PD(30)     157
PD(31)     156
PDMA_      154
PREADY_    145
PRESET_    004
PW_R_      151
P_A(02)    234
P_A(03)    232
P_A(04)    231
P_A(05)    230
P_A(06)    227
P_A(07)    226
P_A(08)    225
P_A(09)    224
P_A(10)    223
P_A(11)    222
P_A(12)    221
P_A(13)    220
P_A(14)    219
P_A(15)    218
P_A(16)    217
P_A(17)    216
P_A(18)    215
P_A(19)    213
P_A(20)    212
P_A(21)    211
P_A(22)    210
P_A(23)    208
P_A(24)    207
P_A(25)    206
P_A(26)    205
P_A(27)    204
P_A(28)    203
P_A(29)    202
P_A(30)    201
P_A(31)    200
ROSCS_     199
RXDATA     002
TXDATA     003
VCC        001
VCC        021
VCC        038
VCC        057
VCC        077
VCC        097
VCC        114
VCC        133
VCC        153
VCC        173
VCC        190
VCC        209
VCC        229
VCC        249
VCC        266
VCC        285

    11.2 Brighton Pin Names/Numbers (listed by number)

     #    Name
---   --------
001   VCC
002   RXDATA
003   TXDATA
004   PRESET_
005   MTST_
006   BRREQ_
007   BRGNT_
008   LEXCPT_
009   LGNT0_
010   LGNT1_
011   LGNT2_
012   GND
013   A_CLK0
014   B_CLK0
015   LREQ0_
016   LREQ1_
017   LREQ2_
018   LW_R_
019   LBLAST_
020   GND
021   VCC
022   LREADY_
023   LADS_
024   PCLK1
025   LAD(00)
026   LAD(01)
027   LAD(02)
028   LAD(03)
029   LAD(04)
030   LAD(05)
031   GND
032   LAD(06)
033   LAD(07)
034   LAD(08)
035   LAD(09)
036   LAD(10)
037   LAD(11)
038   VCC
039   GND
040   LAD(12)
041   LAD(13)
042   LAD(14)
043   LAD(15)
044   LAD(16)
045   LAD(17)
046   GND
047   LAD(18)
048   LAD(19)
049   LAD(20)
050   LAD(21)
051   LAD(22)
052   GND
053   LAD(23)
054   LAD(24)
055   LAD(25)
056   LAD(26)
057   VCC
058   LAD(27)
059   LAD(28)
060   GND
061   LAD(29)
062   LAD(30)
063   LAD(31)
064   LADP0
065   LADP1
066   GND
067   LADP2
068   LADP3
069   LBE0_
070   LBE1_
071   LBE2_
072   LBE3_
073   ID(31)
074   ID(30)
075   COMP
076   GND
077   VCC
078   DI_IN_
079   ID(29)
080   ID(28)
081   ID(27)
082   ID(26)
083   ID(25)
084   GND
085   ID(24)
086   ID(23)
087   ID(22)
088   ID(21)
089   ICB(06)
090   GND
091   ID(20)
092   ID(19)
093   ID(18)
094   ICB(05)
095   ID(17)
096   GND
097   VCC
098   ID(16)
099   ID(15)
100   ICB(04)
101   ID(14)
102   ID(13)
103   GND
104   ID(12)
105   ICB(03)
106   ID(11)
107   ID(10)
108   ID(09)
109   GND
110   ICB(02)
111   ID(08)
112   ID(07)
113   ID(06)
114   VCC
115   GND
116   ICB(01)
117   ID(05)
118   ID(04)
119   ID(03)
120   ICB(00)
121   GND
122   ID(02)
123   ID(01)
124   ICAS1_
125   ID(00)
126   IRAS1_
127   IW_
128   ICAS0_
129   GND
130   IA(11)
131   IRAS0_
132   IA(10)
133   VCC
134   IA(09)
135   IA(08)
136   IA(07)
137   IA(06)
138   IA(05)
139   GND
140   IA(04)
141   IA(03)
142   IA(02)
143   IA(01)
144   IA(00)
145   PREADY_
146   PBE3_
147   PBE2_
148   PBE1_
149   PBE0_
150   PBLAST_
151   PW_R_
152   GND
153   VCC
154   PDMA_
155   PADS_
156   PD(31)
157   PD(30)
158   PD(29)
159   PD(28)
160   PD(27)
161   GND
162   PD(26)
163   PD(25)
164   PD(24)
165   PD(23)
166   PD(22)
167   GND
168   PD(21)
169   PD(20)
170   PD(19)
171   PD(18)
172   GND
173   VCC
174   PD(17)
175   PD(16)
176   PD(15)
177   PD(14)
178   PD(13)
179   GND
180   PD(12)
181   PD(11)
182   PD(10)
183   PD(09)
184   PD(08)
185   GND
186   PD(07)
187   PD(06)
188   PD(05)
189   PD(04)
190   VCC
191   GND
192   C_CLK0
193   GND
194   PD(03)
195   PD(02)
196   PD(01)
197   PD(00)
198   GND
199   ROSCS_
200   P_A(31)
201   P_A(30)
202   P_A(29)
203   P_A(28)
204   P_A(27)
205   P_A(26)
206   P_A(25)
207   P_A(24)
208   P_A(23)
209   VCC
210   P_A(22)
211   P_A(21)
212   P_A(20)
213   P_A(19)
214   GND
215   P_A(18)
216   P_A(17)
217   P_A(16)
218   P_A(15)
219   P_A(14)
220   P_A(13)
221   P_A(12)
222   P_A(11)
223   P_A(10)
224   P_A(09)
225   P_A(08)
226   P_A(07)
227   P_A(06)
228   GND
229   VCC
230   P_A(05)
231   P_A(04)
232   P_A(03)
233   DD(00)
234   P_A(02)
235   DD(01)
236   DD(02)
237   DCB(00)
238   GND
239   DD(03)
240   DD(04)
241   DD(05)
242   DCB(01)
243   DA(00)
244   DA(01)
245   DA(02)
246   DA(03)
247   DA(04)
248   GND
249   VCC
250   DA(05)
251   DA(06)
252   DD(06)
253   DD(07)
254   DD(08)
255   DCB(02)
256   DD(09)
257   GND
258   DD(10)
259   DD(11)
260   DCB(03)
261   DA(07)
262   DD(12)
263   DA(08)
264   DA(09)
265   DD(13)
266   VCC
267   GND
268   DD(14)
269   DCB(04)
270   DCAS0_
271   DD(15)
272   DRAS0_
273   DA(10)
274   DCAS1_
275   GND
276   DA(11)
277   DRAS1_
278   DD(16)
279   DW_
280   DD(17)
281   DCB(05)
282   DD(18)
283   DD(19)
284   GND
285   VCC
286   DD(20)
287   DCB(06)
288   DD(21)
289   DD(22)
290   DD(23)
291   DD(24)
292   GND
293   DD(25)
294   DD(26)
295   DD(27)
296   DD(28)
297   DD(29)
298   DD(30)
299   DD(31)
300   BRINT0_
301   BRINT1_
302   BRINT2_
303   BRINT3_
304   GND

    Appendix B. Mechanical Drawing

    In the following drawings all dimensions are in millimeters. 

    
                                               153______________
        ||||||||||||||||||||||||||||||||||||||||||__________  A
       /                                          \       A   |
 229 =|                                            |= 152 |   |
     =|                                            |=     |   |
     =|                                            |=     |   |
     =|                                            |=     |   |
     =|                                            |=     |   |
     =|                                            |=     |   |
     =|                                            |=     |   |
     =|                                            |=     |   |
     =|                                            |=     |   |
     =|                                            |=     +---|--40.00 +/- 0.20
     =|                                            |=     |   |
     =|                                            |=     |   +--42.60 +/- 0.20
     =|                                            |=     |   |
     =|                                            |=     |   |
     =|                                            |=     |   |
     =|                                            |=     |   |
     =|                                            |=     |   |
     =|                                            |=     |   |
     =|                                            |=     |   |
     =|                                            |=     |   |
     =|                                            |=     |   |
 304 =|                                            |= 77  |   |
       \__________________________________________/_______V__ |
        ||||||||||||||||||||||||||||||||||||||||||________|___V__
                ||
        1     ->||<-0.50                        76

                                                           |  |   |
       ____________________________________________  ______|__V___V_
     _/                                            \_      |
    / \ |||||||||||||||||||||||||||||||||||||||||| / \  ___V____
  _/    ||||||||||||||||||||||||||||||||||||||||||    \_  ____A_____
                                                           A  |   A
                                                           |  |   |
                                           0.35 MIN -------+  |   |
                                           3.60 REF ----------+   |
                                           4.5 MAX ---------------+

    Appendix C. Acronym Glossary

    C

    CFE             Common Front End

    CMOS            Complementary MOS

D

    DMA             Direct Memory Access

    DRAM            Dynamic Random Access Memory

E

    ECC             Error Checking and Correction

I

    I/O             Input/Output

K

    KB              Kilobyte

L

    LSSD            Level Sensitive Scan Design

M

    MB              Megabyte

    MC or MCA       Micro Channel or Micro Channel Architecture

    MMIO            Memory Mapped I/O

N

    NMI             Non-maskable interrupt

R

    RAM             Random Access Memory

    ROS             Read Only Storage

S

    SIMM            Single In-line Memory Module

    SRAM            Static Random Access Memory

T

    TBD             To be determined

V

    VLSI            Very-Large-Scale Integration

    Appendix D. References

    CFE Architecture 1.3

    Intel, i750, i860 & i960 Processors and Related Products, 1993.

    Intel, 80960CA User's Manual, 1989.

    14.1 Trademarks

    Intel and i960 are trademarks of Intel Corporation.

    Last modified: September 11, 1996