CMOS RAM Bank 1

The first 64 bytes of bank 1 is the same as bank 0; for a definition of these bytes, refer to CMOS RAM--Bank 0 

Note: 
Access to the two banks in CMOS RAM is controlled by the bank-control bit in Status Register A (see Status Register A (Hex 00A)) 

System Number (Hex 40-47F) 
Century Byte (Hex 48) 
Wake-up Alarm Date (Hex 49) 
Extended Control Register A (Hex 4A) 
Extended Control Register B (Hex 4B) 
Reserved (Hex 4C-7F) 



System Number (Hex 40-47F)  
   These bytes are read-only and contain a unique 64-bit system identifier number. The identifier is divided into three parts. The first byte is the version number for the real-time clock chip. The next six bytes (index 41 through 46) contain a system-unique identifier. The last byte is the CRC for the first seven bytes. The system identifier for the Server is FFFFF4h. 


Century Byte (Hex 48)  
   This byte is the century and is coded in the same format (binary or BAD) as specified by the date-mode bit. The range of values is from century 00 to century 99. 


Wake-up Alarm Date (Hex 49)  
   This byte contains the alarm setting for a wake-up call to the system. When the date in the real-time clock matches this setting, the Server 95 is automatically powered-on if the alarm is enabled (see'Extended Control Register B (Hex 4B)'). 


Extended Control Register A (Hex 4A)  
   This read/write register controls security and unattended-power features of the Server 95. 
+-----------------------------------------------+
|  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |
|-----+-----+-----+-----+-----+-----+-----+-----|
| BAT | BSY |  R  |  R  | PAC | TF  | WF  |  KF |
+-----------------------------------------------+
 BAT:     Battery status
 BSY:     Clock update in progress
 PAC:     Power active control
 TF:      Tamper evident status
 WF:      Wake-up alarm status
 KF:      Kickstart status
 R:       Reserved

BAT  The battery-status bit is a read-only bit that indicates the output reading of the battery.  When the bit is 1, the output is active. 
 If the battery is enabled, this bit indicates whether the battery is operating correctly.  If the battery is disabled, this bit is always 0. 

BSY   The clock-update-in-progress bit is a read-only bit; the hardware sets this bit to 1 to indicate that the time and date registers are being updated.  The bit is set 125 microseconds before the update cycle; it is reset at the end of the update cycle. 

PAC    The power-active-control bit controls the power supply when the power switch is in the standby mode.  The kickstart feature or the wake-up alarm set this bit to 0 when they power-on the system.  Setting this bit to 1 while the power switch is in the standby mode turns the system power off. 

Note: To determine whether the power switch is in the power-on mode or the standby mode, see Operator Panel Information. 

   When system is powered-on with the power switch, POST sets this bit to 1. While the power switch is in the power-on mode, this bit has no effect on the system operation. 

TF  The tamper-evident-status bit indicates whether the covers have been breached, causing CMOS RAM to be erased and an interrupt to be generated. Setting this bit to 0 clears the interrupt. (The clear-RAM-enable bit must be set to 1 for this status bit to be set to 1). 

WF  The wakeup-alarm-status bit indicates whether the system has been powered-on because of a wakeup alarm.  When the bit is 1, the time matched the alarm setting, the real-time clock has generated a power-on request and a system interrupt. Setting this bit to 0 clears the interrupt. 

Note: This bit and the kickstart-status bit are valid only if the system was not powered-on with the power switch. To determine whether the power switch is in the power-on mode or the standby mode, see Operator Panel Information. 

KF  The kickstart-status bit indicates whether the system has been powered-on because of the kickstart feature.  When the bit is 1, the kickstart feature has generated a power-on request and a system interrupt. Setting this bit to 0 clears the interrupt. 



Extended Control Register B (Hex 4B) 
   This read/write register controls security and unattended-power features of the Server 95. 
+--------------------------------------------------------+
|  7   |  6   |  5   |  4   |  3   |   2   |  1   |  0   |
|------+------+------+------+------+-------+------+------|
| EXT  |  R   |  R   | CLR  |  R   |  TIE  |  WE  |  KE  |
+--------------------------------------------------------+
 EXT:     External battery enable
 CLR:     Clear RAM enable
 WE:      Wake-up alarm enable
 KE:      Kickstart enable
 R:       Reserved

EXT  The external-battery-enable bit controls the source of the battery backup to the real-time clock chip.  When the bit is set to 1, the chip uses an external battery source. 

CLR  The clear-RAM-enable bit controls the tamper evident logic. When this bit is set to 1, the configuration information in CMOS RAM is erased when the covers are breached. When this bit is 0, CMOS RAM is not erased. 

TE  The tamper-evident-interrupt-enable bit determines whether an interrupt is generated if the covers have been breached.  When the bit is set to 1, an interrupt is generated after CMOS RAM has been cleared. 

WE  The wakeup-alarm-enable bit controls whether the real-time clock generates a wakeup alarm when the time matches the wakeup-alarm setting. When the bit is set to 1 and an alarm occurs, the system is powered-on and an interrupt is generated. 

KE  The kickstart-enable bit controls whether serial port A generates power-on request when it receives an incoming call.  When the bit is set to 1 and  a call is received, the serial port causes the system to power-on, and an interrupt is generated. 



Reserved (Hex 4C-7F) 
   These bytes are reserved. 

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