Technical Reference
Realtime Interface Co-Processor
Realtime Interface Co-Processor Multiport
Realtime Interface Co-Processor Multiport/2

Hardware Volume 3
Realtime Interface Co-Processor Multiport/2


TABLE OF CONTENTS

Federal Communications (FCC) Statement

WARNING: This equipment generates, uses, and can radiate radio frequency energy and if not installed and used in accordance with the instructions manual, may cause interference to radio communications. It has been tested and found to comply with the limits for a Class A computing device pursuant to Subpart J of Part 15 of FCC Rules, which are designed to provide reasonable protection against such interference when operated in a commercial environment. Operation of this equipment in a residential area is likely to cause interference, in which case the user, at his own expense, will be required to take whatever measures may be required to correct the interference.

Second Edition (October 1987)

INTERNATIONAL BUSINESS MACHINES PROVIDES THIS PUBLICATION "AS IS," WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Some states do not allow disclaimer of express or implied warranties in certain transactions; therefore, this statement may not apply to you. This publication could include technical inaccuracies or typographical errors. Changes are periodically made to the information herein; these changes will be incorporated in revisions of the publication. IBM may make improvements and/or changes in the product(s) and/or the program(s) described in this publication at any time.

This publication replaces and obsoletes the earlier publication IBM Realtime Interface Co-Processor Technical Reference.

It is possible that this publication may contain references to, or information about, IBM products (machines or programs), programming, or services that are not announced in your country. Such references or information must not be construed to mean that IBM intends to announce such IBM products, programming, or services in your country.

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Copyright International Business Machines Corporation 1987

ABOUT THIS BOOK

Purpose

The hardware volumes of this publication contain technical reference information concerning the hardware of the three feature cards:

Note: The general term "co-processor adapter(s)" is used to designate all three of the feature cards named above. Specific names, as given above, will be used to indicate specific feature cards.

The objectives of the hardware volumes of this publication are to:

Note: Software information can be found in the software volumes that are contained on the other diskettes of this publication package.

Audience

The information in this publication is both introductory and for reference use. It is intended for hardware and software designers, programmers, engineers, and anyone else with a knowledge of electronics and/or programming who needs to understand the use and operation of either the Realtime Interface Co-Processor, the Realtime Interface Co-Processor Multiport, or the Realtime Interface Co-Processor Multiport/2.

It is assumed that the reader is familiar with the co-processor adapter, as well as the system unit, the applications in use, and programming. Therefore, terminology is not explained herein, except for terms that may be specially implemented.

This publication is written for the knowledgeable programmer, designer, or engineer who wishes to understand detailed use and operation of the co-processor adapter.

Organization

The information contained in this volume is organized into four chapters and an appendix:

Related Publications

The library for the Realtime Interface Co-Processor, the Realtime Interface Co-Processor Multiport, and the Realtime Interface Co-Processor Multiport/2 consists of the following publications:

Reference Publications

One or more of the following publications might be needed for reference when using this publication.

Conventions

CHAPTER 1. INTRODUCTION TO THE CO-PROCESSOR ADAPTERS

THE PURPOSE OF THIS CHAPTER

This chapter provides a brief description of the Realtime Interface Co-Processor, the Realtime Interface Co-Processor Multiport, and the Realtime Interface Co-Processor Multiport/2. The chapter may be used as a quick reference guide to their major hardware components, electrical interfaces, and physical interfaces. The information in this chapter is divided into two main topics:

Note: Software information can be found in the software volumes that are contained on the other diskettes of this publication package.

GENERAL PRODUCT DESCRIPTIONS

The Realtime Interface Co-Processor and Realtime Interface Co-Processor Multiport are both single-slot, full-length adapter cards for use in most models of the IBM Industrial Computer and the IBM Personal Computer, while the Realtime Interface Co-Processor Multiport/2 is a single-slot, full-length adapter card for use in most models of the IBM Personal System/2 (PS/2).

Communications Capabilities

These adapter cards provide serial communications capability without degrading the performance of the system unit. The cards serve as an input and output adapter for the system unit. In addition, the cards are programmable, using a self-contained 80186 microprocessor to perform on-board processing.

Standard and optional communications ports are available as follows:

Each port is capable of supporting either half-duplex or full-duplex communications. All ports are under control of a serial communications controller.

Four communications interfaces are available on the Realtime Interface Co-Processor:

On the Realtime Interface Co-Processor Multiport, the four standard ports use only the RS-232-C/V.24 communications interface, while the four optional ports may be either RS-232-C/V.24 or RS-422-A.

The Realtime Interface Co-Processor Multiport/2 provides no ports as standard, however its options include:

All three co-processor adapter cards can support various protocols and electrical connections that might be required.

Processing Power

The three co-processor adapter cards provide processing power through the on-board 80186 processor. This enables the system unit to offload most processing associated with communications.

Typical uses for which the processor can be programmed include the following:

Software Support Functions

The three co-processor adapters provide software support functions for supported user tasks. Included in this software support are:

Direct Memory Access

All three co-processor adapter cards allow for direct memory access (DMA) to or from the serial communications controller on ports 0 and 1.

Random-Access Memory

The three co-processor adapter cards support random-access memory (RAM) as indicated in the chart below.

Note: The upper 64K bytes of card memory (F0000h - FFFFFh) is reserved for 80186 PROM address space and cannot be accessed by the system unit.

Access to the memory on the co-processor adapter is shared with the system unit, which may select any shared page "window" of memory for reading or writing. A VLSI custom gate array controls the memory access contention between the 80186 and the system unit. On the Realtime Interface Co-Processor and the Realtime Interface Co-Processor Multiport, the page "window" is always 8k bytes, while on the Realtime Interface Co-Processor Multiport/2, the page "window" is variable, as indicated in the chart below.
Co-Processor Adapter RAM (Kb) Window (Kb)
Reatime Interface Co-Processor 128, 256,
512, 960
8
Reatime Interface Co-Processor - Multiport 128, 512 8
Reatime Interface Co-Processor - Multiport/2 512, 960 8, 16,
32, 64

HARDWARE COMPONENTS AND CONNECTORS

This section lists major hardware components and physical interfaces on the co-processor adapter cards. These components are described in detail in later chapters and appendixes.
Hardware Components
 Random-access memory (RAM)
 Programmable read-only memory (PROM)
 80186 microprocessor
 8036 CIO
 8030 or 80C30 SCC
 Shared storage interface chip
 Electrical interface boards
 LED indicators

Physical Interfaces
 Co-processor adapter to host system unit
 Communications ports to communications cables
 Co-processor adapter to electrical interface boards
 Address switch*
 Jumpers*
 Co-processor adapter to 8036 CIO
 Co-processor adapter to 8030 SCC
 Communications cables
 Co-processor adapter communications ports wrap plug
 Cable end wrap plugs
* On the Realtime Interface Co-Processor Multiport/2, these functions are performed by the Adapter Description File instead.

It is convenient to view the co-processor adapter hardware in three major groupings as follows:

These major topic groupings are discussed in Chapters 2, 3, and 4, respectively.

CHAPTER 2. CO-PROCESSOR ADAPTER COMPONENTS

THE PURPOSE OF THIS CHAPTER

This chapter describes the details of individual components on the Realtime Interface Co-Processor Multiport/2. Each major component is described in terms of its function, its physical characteristics, and its special features. For those hardware components that are programmable, programming considerations are provided or referenced.

The adapter-related components described in this chapter include:

BLOCK DIAGRAM

The following block diagram shows the interaction of the co-processor adapter components.

          -----
          |   |      --------               ---
          | B |      | OSC  |-->---         |B|                 -----------
          | u |      |25 Mhz|     |         |u|   *<------------|  PROM   |
          | s |      --------     |         |f|   *             -----------
          |   |                   |         |f|   *                  |
          | i |    ---       ------------   |e|   *                  |
          | n |    |B|       |          |<->|r|<->*             -----------
          | t |    |u|       |   CMOS   |   ---   *<------------|  PROM   |
          | e |-<->|f|--<->--|   Gate   |-------- *             -----------
          | r |    |f|       |   array  |-------| *                  |
          | f |    |e|       |          |----- || *                  |
          | a |    |r|       |          |--- | || *                  |
          | c |    ---       ------------  | | || *                  |
          | e |           ---------------- | | || *    ---------     |
          |   |           |Buffer||Buffer| | | || *->--|  Add  |-->---
          -----           ---------------- | | || *    | latch |
                  -----<->-----      |     | | || *    ---------
             --------- ---------     |     | | || *
             |       | |       |     |     | | || *  ----------   ---------
             |  RAM  | |  RAM  |     |     | | || *  | 80186  |-<-| OSC   |
             |       | |       |-<->--     | | || ****  CPU   |   |14.74  |
             |       | |       |           | | || *  |        |   |Mhz    |
             |       | |       |           | | |- * -|2 DMA   |   ---------
             --------- ---------           | | |  *  |3 Timers|
                                           | | |  *  ----------
                                           | | |  *
                                           | | |  *
                                           | | |  *
               ----------         -----    | | -- * -----------------------
               | Scalar |         |LED|----| |    *                       |
               ----------         -----    | ---- * -------               |
                   |                       |      *       |               |
                   |       -----------     |      *  -------------------- |
                   |       |  Z8036  |     |      *  | DMAREQ           | |
                   |       | CIO (x2)|     |      **** Z8030 SCC (x4)   | |
                   |       |         |     |      *  |8 Serial channels | |
                   ---->---| Watchdog|-->---      *  |                  | |
                           |  timer  |            *  -------------------- |
                           |         **************      |                |
                           | 2 Ports |            *      |     ---------- |
                           | 3 Timers|            *      --<->-|  Remote|--
                           |         |            *            |  clock |
                           |  PA  PB |            **************        |
                           -----------                         |  EIB   |
           ** Legend **       |   ---------------<->-----------|        |
          Bidirectional       |                                ----------
            Bus    ***        ----------------<->-------------------
            Signal <->

RANDOM-ACCESS MEMORY (RAM)

Functions

Random access memory (RAM) on the Realtime Interface Co-Processor Multiport/2 provides 512 KB or 1 Megabyte of on-board read/write storage space and is provided in two SIP packages. That storage space can be accessed by the resident 80186 co-processor adapter or by the system unit through the Micro-Channel interface of the Shared Storage Interface Chip.

The Shared Storage Interface Chip serves as the dual-ported RAM controller arbitrating RAM requests from the 80186 co-processor and the system unit processor. It also provides other RAM support features including:

The system unit can access all on-board RAM storage (except that reserved for PROM) in either 8, 16, 32, or 64K-byte windows. The window size and location are selected through the Shared Storage Interface Chip either by the system unit or by the on-board 80186.

The Shared Storage Interface Chip guarantees the RAM cycle time to be 300 nanoseconds, which provides a maximum data rate of 6.66 megabytes per second from the RAM. This is not to say that either processor can access the RAM this fast; however, each processor "holds" the RAM for only 300 nanoseconds, then "releases" it. Thus the other processor is allowed access if needed.

Self-diagnostics in the on-board PROM test the RAM for size, addressability, and parity. These diagnostic test modules may be invoked by user tasks on the co-processor adapter. The interfaces are defined in "Diagnostic Test Modules," found on another diskette in this publication package.

Physical Characteristics

Two dynamic RAM SIPS (256K X 9 or 512K X 9) with 120-nanosecond access time are used on this adapter.

Information on all configurations is found in the Guide to Operations and the Hardware Maintenance and Service manuals.

RAM/PROM Memory Map

The upper 64K (F0000h - FFFFFh) of card memory is reserved for 80186 PROM address space and cannot be accessed by the system unit. A typical RAM/PROM memory map is shown below.

    Address             Bytes
    -------- --------- --------
     FFFFF   |       |
             | PROM  | Reserved for 80186 PROM address space
     FC000   |       |
    -------- |-------| --------
     FBFFF   |       |
             | PROM  | Reserved for 80186 PROM address space
     F0000   |       |
    -------- |-------| --------
     EFFFF   |       | 960K
             |  RAM  |
     80000   |       |
    -------- |-------| --------
     7FFFF   |       | 512K
             |  RAM  |
     40000   |       |
    -------- |-------| --------
     3FFFF   |       | 256K
             |  RAM  |
     20000   |       |
    -------- |-------| --------
     1FFFF   |       | 128K
             |  RAM  |
     00000   |       |
    -------- --------- --------

PROGRAMMABLE READ-ONLY MEMORY (PROM)

Functions

The upper 64K bytes of card memory is reserved for the on-board read-only memory (PROM) address space and cannot be accessed by the system unit. (Refer to "RAM/PROM Memory Map".) This co-processor adapter provides 16K bytes of PROM, of which approximately 8K bytes are occupied by microcode consisting of a Bootstrap Loader, a set of "Diagnostic Test Modules," and a set of "PROM Services." (Refer to another diskette in this package for the above-named modules.)

Physical Characteristics

The Realtime Interface Co-Processor Multiport/2 PROM standard components are two 28-pin 27C64 PROMs (250 nanosecond access time).

Power-On Self-Test (POST)

Power-on diagnostics perform a checksum verification on PROM, among other diagnostic tests. A checksum test can also be performed on PROM by a user task invoking the checksum diagnostic routine. The interfaces are defined in "Diagnostic Test Modules," located on another diskette in this package.

80186 MICROPROCESSOR

Functions

The Intel 80186 is the microprocessor on the co-processor adapter:

Physical Characteristics

The 80186 microprocessor has the following physical characteristics:

Programming Considerations

Standard programming of the 80186 is described in detail in the Intel user's documentation and is not included here. Guidelines are provided in this subsection for certain features that:

80186 Hardware Interrupt Lines

Five possible interrupt lines exist on the 80186. Their definitions and pin numbers are as follows:
Signal Name Signal Pin # Description and Assignment
NMI 46 Non-Maskable Interrupt (Used for parity error, watchdog, NMI command, lost refresh, parity channel check, Ctrl-Alt-Del)
INT0 45 Shared storage interface chip interrupt
INT1 44 Z8030-SCC and Z8036-CIO interrupts
INT2 42 Not used
INT3 41 INT acknowledge for SCC and CIO

The 80186 uses internal interrupt vectors for NMI (Non-Maskable Interrupts) and INT0. In the case of INT1, the 8030 Serial Communications Controllers and 8036 CIOs provide the interrupt vectors. The 8030's and 8036's decide, via hardware, which device supplies the vector during the interrupt acknowledgement cycle. The interrupt priority is as follows:
Highest SCC0 U2 - Supports ports 0 and 1
  SCC1 U3 - Supports ports 2 and 3
  CIO0 U6 - Supports ports 0 and 1
  CIO1 U7 - Supports ports 2 through 7
  SCC2 U4 - Supports ports 4 and 5
Lowest SCC3 U5 - Supports ports 6 and 7

The only thing that a task should ever do to the interrupt controller is to issue a non-specific End Of Interrupt (EOI) command. Any other command or change could lead to unpredictable results.

After any hardware interrupt, this register must be written to enable more interrupts on the priority that last interrupted or on a lower priority. The only EOI command that should be issued is the non-specific EOI. This is done by writing 8000h to I/O port FF22h.

Example:

   MOV   AX,8000h    ;Set data value for non-specific EOI
   MOV   DX,0FF22h   ;Set I/O address
   OUT   DX,AX       ;Issue EOI

80186 Interrupt Register Addresses

The following chart provides a summary of the 80186 Interrupt Controller Registers and their respective addresses:

                                        Address
     ----------------------------------
     |   INT3 Control Register        | FF3Eh
     |--------------------------------|
     |   INT2 Control Register        | FF3Ch
     |--------------------------------|
     |   INT1 Control Register        | FF3Ah
     |--------------------------------|
     |   INT0 Control Register        | FF38h
     |--------------------------------|
     |   DMA 1 Control Register       | FF36h
     |--------------------------------|
     |   DMA 0 Control Register       | FF34h
     |--------------------------------|
     |   Timer Control Register       | FF32h
     |--------------------------------|
     |   Interrupt Status Register    | FF30h
     |--------------------------------|
     |   Interrupt Request Register   | FF2Eh
     |--------------------------------|
     |   In-Service Register          | FF2Ch
     |--------------------------------|
     |   Priority Mask Register       | FF2Ah
     |--------------------------------|
     |   Mask Register                | FF28h
     |--------------------------------|
     |   Poll Status Register         | FF26h
     |--------------------------------|
     |   Poll Register                | FF24h
     |--------------------------------|
     |   EOI Register                 | FF22h
     ----------------------------------

Be aware that the Realtime Interface Co-Processor Multiport/2 uses two types of standard interrupts. The 8030 and 8036 chips supported operate on INT1 in Cascade Mode. The Shared Storage Interface Chip operates on INT0 and runs in Fully Nested Mode. INT0 must run in edge-triggered mode and INT1 must run in level-triggered mode.

Wait State Generator

The 80186 can be programmed to provide 'READY' or 'WAIT' state generation for both (or either) memory or I/O peripherals. Memory (PROM and RAM) is programmed to insert zero 'WAIT' states, and use external 'READY' signal, which is controlled by the Shared Storage Interface Chip. Peripherals are programmed for one 'WAIT' state and the external 'READY' signal is also accepted. The wait bits are located in bits 2, 1, and 0 of the MPCS, UMCS, and PACS registers.

The following table shows the memory and peripheral chip-select register addresses:
Register I/O Address Register Type
MMCS FFA6h Mid-range Memory Chip-Select
LMCS FFA2h Lower Memory Chip-Select
UMCS FFA0h Upper Memory Chip-Select
PACS FFA4h Peripheral Chip-Select
MPCS FFA8h Peripheral Chip-Select

DMA Channels, Allocation, and Registers

The two DMA channels are integrated into the 80186. The registers to control them are documented in the 80186 literature. Because there are four requesting sources (two for each SCC channel), a DMA steering multiplexer is implemented. The following I/O register controls the multiplexer:

             I/O Address = 0084h
   -----------------------------------------
   | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
   -----------------------------------------
      |    |    |    |    |    |    |    |      -
      |    |    |    |    |    |    |    ----O  |
      |    |    |    |    |    |    ---------O  | Set and used
      |    |    |    |    |    --------------O  | by PROM only
      |    |    |    |    -------------------1  |
      |    |    |    |                          -
      |    |    |    |                          -
      |    |    |    ------------------------R0 |
      |    |    -----------------------------R1 | DMA steering
      |    ----------------------------------R2 | bits
      ---------------------------------------R3 |
- The DMA allocation logic (DAL) assigns the two DMA channels (DRQ0 and DRQ1) on the 80186 to two of the four SCC request sources. The four possible DMA requests come from the SCC: channel A transmit (TxREQA), channel B transmit (TxREQB), channel A receive (RxREQA), and channel B receive (RxREQB). The 80186 can write or read the DAL.

The hardware makes no attempt to handle possible conflicting values between R0,R1, and R2,R3 (such as R3 R2 R1 R0 = 0000).

   -----------          -----------            -------------
   |  80186  |          |  DMA    |    TxREQ   |------     |
   |         |   DRQ0   |  Alloc. |<-----------|     |     |
   |       19|<---------|  logic  |<-----------|  A  |     |
   |         |          |         |    RxREQ   |     |  S  |
   |         |   DRQ1   |         |            |-----|  C  |
   |       20|<---------|  (MUX)  |    TxREQ   |     |  C  |
   |         |          |         |<-----------|  B  |     |
   |         |          |         |<-----------|     |     |
   | 27      |          |         |    RxREQ   |------     |
   -----------          |---------|            |           |
      |  -------------->|  Latch  |<--         |           |
      |    Data Bus     -----------  |         -------------
      |                              |
      --------------------------------
                PCS1
DMA steering bit definitions are as follows:

80186/DMA Channel 0 Assignment

----------------------------------------
|  R1 |  R0 |  SCC Requesting Source   |
|-----+-----+--------------------------|
|  0  |  0  |  Transmit channel A      |
|  0  |  1  |  Receive channel A       |
|  1  |  0  |  Transmit channel B      |
|  1  |  1  |  Receive channel B       |
----------------------------------------
80186/DMA Channel 1 Assignment
----------------------------------------
|  R3 |  R2 |  SCC Requesting Source   |
|-----+-----+--------------------------|
|  0  |  0  |  Transmit channel A      |
|  0  |  1  |  Receive channel A       |
|  1  |  0  |  Transmit channel B      |
|  1  |  1  |  Receive channel B       |
----------------------------------------

When using DMA, the SCC should always be enabled by the WR0 register (see "SCC Register Addressing and Usage") before enabling the DMA channel through the DMA control word register.

The 80186 DMA registers and DAL register settings are accomplished through the DMACONNECT PROM Service (INT AAh). (Refer to "PROM Services" on another diskette in this publication package).

The DMA registers are located at FFC0h - FFCAh for channel 0 and FFD0h - FFDAh for channel 1. Refer to Intel 80186 publications for a detailed description of the DMA registers. PROM Services may be used to program the DMA so you should never have to access the DMA registers directly. The DMA registers are as follows:

     -----------------------------------------------
     |                     | I/O Register Address  |
     | DMA Register Name   |-----------------------|
     |                     | Channel 0 | Channel 1 |
     |---------------------+-----------+-----------|
     |                     |           |           |
     | Control word        |   FFCAh   |   FFDAh   |
     |                     |           |           |
     | Transfer count      |   FFC8h   |   FFD8h   |
     |                     |           |           |
     | Destination pointer |   FFC6h   |   FFD6h   |
     |  (upper four bits)  |           |           |
     |                     |           |           |
     | Destination pointer |   FFC4h   |   FFD4h   |
     |                     |           |           |
     | Source pointer      |   FFC2h   |   FFD2h   |
     |  (upper four bits)  |           |           |
     |                     |           |           |
     | Source pointer      |   FFC0h   |   FFD0h   |
     |                     |           |           |
     -----------------------------------------------

Hardware Timers

The three 80186 timers are reserved for use by the Realtime Control Microcode. Refer to the software section of this publication package for further details.

The timer I/O addresses are as follows:

     ---------------------------------------------------
     |                   |       Register Address      |
     | Control Register  |-----------------------------|
     |                   | Timer 0 | Timer 1 | Timer 2 |
     |-------------------+---------+---------+---------|
     |                   |         |         |         |
     | Mode/control word |  FF56h  |  FF5Eh  |  FF66h  |
     |                   |         |         |         |
     | Max count B       |  FF54h  |  FF5Ch  |   --    |
     |                   |         |         |         |
     | Max count A       |  FF52h  |  FF5Ah  |  FF62h  |
     |                   |         |         |         |
     | Count register    |  FF50h  |  FF58h  |  FF60h  |
     |                   |         |         |         |
     ---------------------------------------------------

Peripheral Control Block Programming

The 80186 peripheral control block is set up by the power-on self-test (POST). It is located in I/O space at address FF00h - FFFFh. The only areas of the Peripheral Control Block that may be modified are the DMA descriptors and interrupt controller registers. Modifying anything else will cause unpredictable results.

8030 SERIAL COMMUNICATIONS CONTROLLER (SCC)

Functions

The primary function of the two 8030 and (up to) two 80C30 Serial Communications Controllers (SCCs) is to provide controller logic for eight independent serial communications ports.

After initial configuring of the 8030s by the Realtime Control Microcode, most of the serial communications workload is relieved from the 80186 processor and is performed by the 8030s. (Refer to the appropriate Zilog publication for a detailed description of the 8030 Serial Communications Controller.)

The Serial Communication Controllers (8030 and 80C30) provide many versatile features, such as:

The Serial Communication Controllers come in two packages:

This chip is programmed to satisfy special serial communications requirements and support standard communications protocols. Each communications port has a transmitter section and a receiver section and may be run in a full-duplex or half-duplex mode of operation. Each of the ports supports a communication port. For information on the individual ports, refer to " Electrical Interface Boards".

Microcode

Diagnostics are provided for the SCC. For diagnostic testing, the Serial Communications Controller is run in an internal data wrap mode, at various baud rates and bit modes. The SCC test routine is called by the power-on self-test (POST) and is callable by a user. (See "Diagnostic Test Modules," located on another diskette in this publication package.)

Physical Characteristics

The Serial Communications Controllers provide controller logic for each of the four, six or eight ports on the co-processor adapter. The SCC interfaces to the following components on the co-processor adapter:

The block diagram shown at the beginning of this chapter provides an overview of the interconnections.

The "Interrupt Table Vector Map," found on another diskette in this publication package, gives information on interrupt vector assignments.

8030 and 80C30 Pin Functions

Each of the SCCs uses a single +5 volt power supply.

This section describes the pin functions.

                 --------------------
           - <-->| AD7      TxDA    |---> -               -
           | <-->| AD6      RxDA    |<--- -Serial data    |
  Address/ | <-->| AD5      TRxCA   |<--> -               |
  data bus | <-->| AD4      RTxCA   |<--- -Port clocks    |
           | <-->| AD3      SYNCA   |<--> -               | Port
           | <-->| AD2      W/REQA  |---> |               |  A
           | <-->| AD1      DTR/REQA|---> |Port controls  |
           - <-->| AD0      RTSA    |---> |for modem, DMA,|
Bus timing - --->| AS       CTSA    |<--- |or other       |
 and reset - --->| DS       DCDA    |<--- -               -
           - --->| R/W      TxDB    |---> -               -
   Control | --->| CS1      RxDB    |<--- -Serial data    |
           - --->| CS0      TRxCB   |<--> -               |
           - <---| INT      RTxCB   |<--- -Port clocks    |
           | --->| INTACK   SYNCB   |<--> -               | Port
 Interrupt | --->| IEI      W/REQB  |---> |               |  B
           - <---| IEO      DTR/REQB|---> |Port controls  |
                 |          RTSB    |---> |for modem, DMA,|
                 |          CTSB    |<--- |or other       |
                 |          DCDB    |<--- -               -
                 --------------------
                   ^      ^       ^
                  +5V    GND     PCLK

SCC Register Bit Definition

-------------------------------------------------------
|D15|D14|D13|D12|D11|D10|D9|D8|D7|D6|D5|D4|D3|D2|D1|D0|
-------------------------------------------------------
  |   |   |   |   |   |  |  |  |  |  |  |  |  |  |  |
  |   |   |   |   |   |  |  |  |  |  |  |  |  |  |  --- PLL/32-0
  |   |   |   |   |   |  |  |  |  |  |  |  |  |  ------ Local-0
  |   |   |   |   |   |  |  |  |  |  |  |  |  --------- DCE/DTE-0
  |   |   |   |   |   |  |  |  |  |  |  |  ------------ PLL/32-1
  |   |   |   |   |   |  |  |  |  |  |  --------------- Local-1
  |   |   |   |   |   |  |  |  |  |  ------------------ DCE/DTE-1
  |   |   |   |   |   |  |  |  |  --------------------- Reserved
  |   |   |   |   |   |  |  |  ------------------------ Reserved
  |   |   |   |   |   |  |  --------------------------- 0
  |   |   |   |   |   |  ------------------------------ Reserved
  |   |   |   |   |   --------------------------------- 0
  |   |   |   |   ------------------------------------- Reserved
  |   |   |   ----------------------------------------- 0
  |   |   --------------------------------------------- Reserved
  |   ------------------------------------------------- 0
  ----------------------------------------------------- Reserved

Clocking and Timing

The SCC peripheral clock (PCLK) has an operating frequency of 7.3728 Mhz to support most serial communication line speeds to 0.01% tolerance.

External clocking normally must be used for transmission rates greater than 38.4K baud. However, even higher rates can be achieved using internal clocking under various conditions.

Phase Locked Loop: Using the SCC phase locked loop is normally a problem because the phase locked loop must run at 16 or 32 times the data rate. The receive clock source must be the output of the digital phase locked loop. Since the SCC allows the baud rate generator to exit the chip via the TRxC pin, the transmitter clocking is implemented by an external divider to divide the baud rate generator clock by either 16 or 32. Thus the transmitter clocking is provided by the RTxC pin. This is implemented on Ports 0 and 1 only.

The divisor is selected by certain bits in POS4 and POS5 registers. Once written by POS, these bits may be read via POS or the SCCREG(880H). See the SCCREG section of the Shared Storage Interface Chip appendix. To implement this, the following steps must be taken:

  1. Program to the correct divisor (16 or 32, depending on the encoding method for which the digital phase locked loop is programmed). Set PLL/32 to 1 for a divisor of 32. Set PLL/32 to 0 for a divisor of 16. Set LOCAL to 1.
  2. Program the baud rate generator to the correct baud rate for the digital phase locked loop (WR12 & WR13).
  3. Program the transmit clock (TRxC) pin as an output, the source of the transmit clock pin to be the baud rate generator, the transmitter clock source to be the RTxC pin, and the PLL receive clock source to come from the DPLL output (WR11=66H).
  4. Program the PPL clock source to come from the BRG output (WR14=100X X111 binary, where X can be either 0 or 1).
  5. Verify on the electrical interface board that remote clock 2 does not conflict with the TRxC driver.
If the port is to use external clocking on the SCC RTxC pin, then program LOCAL to a 0 (for remote). PLL/32 will be a don't care.

Internal and External Clocking:

The SCC in conjunction with the Realtime Interface Co-Processor Multiport/2 has a complex clocking system. The user is allowed to use any combination of programming and hardware options to achieve the desired clocking option. The only restriction on hardware is that two outputs do not "drive" each other.

Internal SCC Clocking Block Diagram:

                OSC Select
              (WR11 - D7 = 0)
                    |
       -------------o
-SYNC  |         -------
 oo----+----o----|1    |                                       RxD
       |    |    |     |          -------           ---------o--oo
    -----   |    |   M |          |     |           |        |
   -| I |o---    |     |--------o-|00   |        --------    |
   |-----        |     |  ------+-|01 M | RxD CLK|  Rx  |--- |
   |           --|0    |  | ----+-|10   |--------| Unit |  | |
   |           | -------  | | --+-|11   |        |      |- | |
   |    -----  |          | | | | |     |        --------| | |
oo-o----| I |o--          | | | | -------   --------     | | |
-RTxC   -----             | | | |           | Clock|-----o | |
                          | | | |           | Rate |-----+-o |
               -----      | | | |           --------     | | |
 oo------o-----| I |o---- | | | | -------                | | | TxD
-TRxC    |     -----    | | | | | |     |          ------+-+-+--oo
         |              | | | | o-|00   |       -------- | | |
         |              --o-+-+-+-|01 M |TxD CLK|  Tx  |-- | |
Tx DPLL--+------------------+-+-+-|11   |---o---| Unit |   | |
CLKOUT   |                  o-+-+-|10   |   |   |      |---- |
         |        -------   | | | |     |   |   --------     |
         |        |     |   | | | -------   |                |
         |        |   00|---+-+-o           |                |
         |  ----- | M 01|---+-+-+------------                |
         --o| I |-|   10|---o | |             ----------------
            ----- |   11|---+-o | -------     |
              |   |     |   | | | |     |     |  ------
              |   -------   | | o-|101  |     ---|    |--- Tx DPLL
              |     | |     | | | |    M| -----  |DPLL|    CLKOUT
           Echo controls    | | | |     |-| I |o-|Unit|
        (WR11 - D2, D1, D0) o-+-+-|100  | -----  |    |
                            | | | |     |        |    |--- Rx DPLL
                            | | | -------        ------    CLKOUT
                            | | |     |
                            | | |     ----------- DPLL CLK Select
BRG CLKOUT ------------------ | |                (WR14 D7, D6, D5)
                              | | -------
Rx DPLL CLKOUT ---------------- | |     |
                                --|0    |    ------
                                  |   M |    |    |
PCLK      -----                   |     |----|BRG |---- BRG CLKOUT
oo--------| I |o------------------|1    |    |Unit|
          -----                   |     |    ------
                                  -------
                                     |
                              BRG CLK Select
                               (WR14 - D1)

where:
   M = Multiplexer
   oo = External pin
   BRG = Baud Rate Generator
   DPLL = Digital Phase Locked Loop
   Clock Rate = 1, 16, 32, or 64 x Data Rate Selector

External SCC Clocking Block Diagram:

                                          EIB
     SCC                                 +---------------------+
--------------                           |                     |
|            |                 RMTCLK2   |       ---Tx OUT CLK |
|       TRXC |------------o-------------------o--|D|--------oo |
|       RTXC |----        |              |    |  ---           |
|            |   |        |  DCE/DTE CLK | +E---               |
|            |   |        | -----------------|B|               |
|            |   |        | |            |   ---               |
|            |   |        | |            |    |  ---Tx IN CLK  |
|            |   |        | |            |    ---|R|--------oo |
|            |   |        | |            |       ---           |
--------------   |        | |            |                     |
                 |        | |            |                     |
                 |        | |            |       ---Rx IN CLK  |
                 |        | |     ---------------|R|--------oo |
                 |        | |     |      |       ---           |
                 |        | |     |      |                     |
                 |        | |     |      +---------------------+
                 |        | |     |
                 ---------+-+-----+-----------------
SSTIC                     | |     |                |
+-------------------------|-|-----|----------------|-------+
|  SCC REG                | |     |                |       |
|                         | |     |                |       |
| ------ PLL/32       ----+-+-----+--------        |       |
| |D0/3|--------------+-- | |     |       |        |       |
| |    | LOCAL        | | | |     |    --------    |       |
| |D1/4|--------------- | | |     -----|0     |    |       |
| |    | DCE/DTE CLK    | | |          |   M  |-----       |
| |D2/5|----------------+-+--          |      |            |
| |    |       ---------+--    --------|1     |            |
| |    |       |        |      |       --------            |
| ------ ------o        |      |                           |
|        | ---------    |      |                           |
|        | |PLL/16 |---------  |                           |
|        | ----------|0     |---                           |
|        |           |   M  |                              |
|        | ----------|1     |                              |
|        --|PLL/32 |-|      |                              |
|          --------- --------                              |
|                                                          |
+----------------------------------------------------------+


   B = Buffer/Driver - with positive enable
   M = 2-to-1 Multiplexer
   R = Line Receiver
   D = Line Driver
   oo = External pin

Line Speed and Performance

The co-processor adapter is designed to support 19.2K bits per second (bps) full duplex asynchronous protocol on all ports. Full duplex HDLC/SDLC protocols are supported up to the following speeds:

Although all ports will support 19.2K bps full duplex asynchronous protocol, all eight ports cannot support it simultaneously. Similarly, the speeds listed above for full duplex HDLC/SDLC protocols are not all supported simultaneously. Because there are up to eight ports on the co-processor adapter, the limiting factor on line speeds is not an aggregate data rate, but rather the number of interrupts per second that the 80186 must handle. The number of interrupts varies depending on several factors: Example 1

Suppose you want to support eight lines all in character interrupt mode asynchronous protocol with:

The number of interrupts would be calculated as follows:
    (2 x 19,200 x 2) / 10 = 7,680.00
    (1 x 19,200 x 2) / 11 = 3,490.90
    (3 x  3,600 x 2) / 12 = 1,800.00
    (2 x  3,600 x 2) / 11 = 1,309.09
                           ---------
              Total        14,279.99 interrupts per second
The combination of lines in this example would work, as would all other combinations with fewer than 14,279.99 interrupts per second, if other concurrent interrupting activity is kept to a minimum.

Note:
For Example 1, frame size was counted as being:

       1 start bit,
       some number of data bits (5, 6, 7 or 8),
       some number of stop bits (1, 2, or 1 and 1/2), and
       0 or 1 parity bit.
A 10-bit frame could be:
       7 data bits,
       1 parity bit,
       1 stop bit, and
       1 start bit;
or it could also be:
       6 data bits,
       2 stop bits,
       1 start bit, and
       1 parity bit.
Example 2

If you change the combination of lines from Example 1 such that three of the 3600 bps lines have 11-bit frames and only two of the 3600 bps lines have 12-bit frames, the number of interrupts would be calculated as follows:

       (2 x 19,200 x 2) / 10 =  7680.00
       (1 x 19,200 x 2) / 11 =  3490.90
       (2 x  3,600 x 2) / 12 =  1200.00
       (3 x  3,600 x 2) / 11 =  1963.64
                              ---------
                 Total        14,334.54 interrupts per second
The combination of lines in this example would not work. Nor would any other combinations with greater than or equal to 14,334.54 interrupts per second.

Using DMA obviously can enhance performance; however, the smaller the I/O block the more DMA becomes like character interrupt mode. When the I/O block contains only one character, DMA and character interrupt mode are virtually identical.

The host system unit in which the co-processor adapter resides does not affect its internal line speed performance. It does, however, affect the speed with which data can be transferred between the host and the co-processor adapter, since different hosts have different performance in terms of accessing memory.

Line Speeds Supported

The serial interface line speeds that are supported by the co-processor adapter are shown in the following table:

Line
Speed
(bps)
RS-232-C RS-422-A
Async Sync Async Sync
110 X

    
X

  
300 X

    
X

  
600 X

    
X

  
1200 X X X X
2400 X X X X
4800 X X X X
7200 X X X X
9600 X X X X
19200 X X X X
38400 X X X X
48000

    

    

    
X
56000

    

    

    
X
64000

    

    

    
X

Notes:

  1. Internal co-processor adapter clocking may be used for baud rates up to 38.4K bps. Generally, external clocking for baud rates greater than 38.4K bps must be provided by the user.

  2. External clocking may be used for any baud rate if the electrical interface adapter provides for remote clocking. Synchronous data rates above 19.2K may require DMA.

Programming Considerations

Refer to the appropriate Zilog publication for a detailed description of the 8030 and 80C30 Serial Communications Controllers.

The SCC has programmable registers. The registers allow you to enable and disable various modes of operation. The SCC should be operated in left shift mode, which is set through SCC write register zero. The power-on self-test (POST) initializes each to operate in shift left mode.

The following PROM Services are provided to support the SCC:

INT A2h Reset the SCC port to the hardware default configuration.
INT A4h General SCC register read/write.
INT AAh Connect two of four SCC DMA request outputs to two 80186 DMA request inputs.
INT ACh Configure and initialize DMA transfer types (I/O-to-memory, memory-to-memory, etc.).
INT AEh Read or write 12-byte DMA table to define DMA transfer source, destination, and byte count.
INT B0h Stop DMA transfer.

(For details, refer to "PROM Services," found on another diskette in this publication package.)

The SCC can also be reconfigured by using the SCC diagnostic subroutine.
INT FEh Reset the SCC port to the default software configuration.

(For details refer to "Diagnostic Test Modules," found on another diskette in this publication package.)

In preparation for programming, the SCC see "PROM Services," located on another diskette in this package.

The Realtime Control Microcode is designed to initialize and manage the SCC; however, if you need to re-program the SCC, the SCCREGS PROM Service (INT A4h) must be used. All possible functions and features of the SCC are not possible on the co-processor adapter. Some of the write register bits must always be either on or off to support DMA and interrupts. These bits are specified under "SCC Register Addressing and Usage".

The communication lines supported by the two base card SCCs (ports 0-3) and the two electrical interface board SCCs (ports 4-7) are defined as follows:
GTxD Gated Transmit Data Serial Output (gated by CIO PA bit - see below)
RxD Receive Data Serial Input
-CTS Clear-to-Send or General Purpose Input
-DCD Data Carrier Detect or General Purpose Input
-RTS Request-to-Send or General Purpose Output
-RxCLK Receive Clock Input (ports 0 and 1 only)
-TxCLK Transmit Clock Input/Output (ports 0 and 1 only)
-DTR Data Terminal Ready or General Purpose Output

Each Tx data is gated by a port address bit from the CIO as shown below. A logical zero on the bit is necessary for Tx data to pass.

    TxD                           -----------
  ------------------------------->|         |
                                  |         |
                  +5V--           |   OR    |
                ------------      |         |     GTxD
                | 6.8k ohm |      |         |--------------->
                | resistor |      |         |
  CIO PA bit    ------------      |         |
  ------------------------------->|         |
                                  -----------
For more information on gating TxD, refer to "Service Interrupts" located on another diskette in this package.

Other communication signals are handled through the 8036 CIO (see "8036 Counter/Timer and Parallel I/O Unit (CIO)")

SCC (8030) Write Registers

There are 16 one-byte write registers for each SCC port which are programmed by the Realtime Control Microcode to configure the functional personality of the ports. The following description provides a summary of the programmable options used to configure the functional personality. Addressing for all data and control registers associated with the SCC is direct. The Realtime Control Microcode issues a series of commands to initialize the desired mode of operation. The interrupt mode is then set. The final action required is to set receiver or transmitter enable.

The SCC write registers are named WR0 through WR15. WR2 and WR9 are shared between ports A and B on that particular SCC.

Some of the program selectable options for configuring the 8030 functional "personality" are as follows:

SCC (8030) Read Registers

Nine read registers are associated with each port of the SCC. Status and data information is obtained by reading these registers. Four of these registers are used for reading status information. Two registers are used for obtaining information on the baud rate generator time constant. One register contains interrupt vector information. Interrupt pending information is contained in another register. A final register acts as a receive buffer.

The readable registers are named RR0 through RR3, RR8, RR10, RR12-13, and RR15.

SCC Register Addressing and Usage

The base addresses of the SCCs are:
Device Address

  
SCC-0 100h Supports ports 0 and 1
SCC-1 400h Supports ports 2 and 3
SCC-2 600h Supports ports 4 and 5
SCC-3 700h Supports ports 6 and 7

Write Registers:

-----------------------------------------------------------------------
|        |Port A|Port B|                                              |
|Register|Offset|Offset|Function                                      |
|--------+------+------+----------------------------------------------|
| WRO    |0020h |0000h |Command register configuring various modes    |
|        |      |      |(select shift left).                          |
|        |      |      |                                              |
| WR1    |0022h |0002h |Interrupt conditions to specify wait or DMA.  |
|        |      |      |Bits 5 and 6 of that register should always   |
|        |      |      |be 1 to define this as a DMA receive request. |
|        |      |      |                                              |
| WR2*   |0024h |0004h |Interrupt Vector.  Used only by the Realtime  |
|        |      |      |Control Microcode, this register can lead to  |
|        |      |      |unpredictable results if modified.            |
|        |      |      |                                              |
| WR3    |0026h |0006h |Receiver parameters which are user-controlled.|
|        |      |      |                                              |
| WR4    |0028h |0008h |Transmit/receive parameters.                  |
|        |      |      |                                              |
| WR5    |002Ah |000Ah |Transmit parameters.  Bit 7 must always be 0  |
|        |      |      |to eliminate DMA requests.                    |
|        |      |      |                                              |
| WR6    |002Ch |000Ch |Sync character 1 or SDLC address.             |
|        |      |      |                                              |
| WR7    |002Eh |000Eh |Sync character 2 or SDLC flag.                |
|        |      |      |                                              |
| WR8    |0030h |0010h |Transmit data buffer.                         |
|        |      |      |                                              |
| WR9*   |0032h |0012h |Master control/reset interrupt.  Used only by |
|        |      |      |the Realtime Control Microcode, this register |
|        |      |      |should never be modified by the user.         |
|        |      |      |                                              |
| WR10   |0034h |0014h |Miscellaneous transmit/receive control bits.  |
|        |      |      |                                              |
| WR11   |0036h |0016h |Clock mode control. Bit 7 (no crystal) should |
|        |      |      |always be set to zero since no crystal is     |
|        |      |      |connected to the receiver clock input.        |
|        |      |      |                                              |
| WR12   |0038h |0018h |Time constant low.                            |
|        |      |      |                                              |
| WR13   |003Ah |001Ah |Time constant high.                           |
|        |      |      |                                              |
| WR14   |003Ch |001Ch |Miscellaneous control bits.  Bit 2 represents |
|        |      |      |transmit DMA request and should always be set |
|        |      |      |to 1.  It cannot function as DTR on ports 0   |
|        |      |      |and 1 since DTR/REQ pin is connected to the   |
|        |      |      |DMA request logic.                            |
|        |      |      |                                              |
| WR15   |003Eh |001Eh |External status control.                      |
-----------------------------------------------------------------------
* Register is shared between ports and may be accessed through either channel.

Read Registers:

-----------------------------------------------------------------------
|        |Port A|Port B|                                              |
|Register|Offset|Offset|Function                                      |
|--------+------+------+----------------------------------------------|
| RRO    |0020h |0000h |Transmit/receive and external status          |
|        |      |      |                                              |
| RR1    |0022h |0002h |Special receive status                        |
|        |      |      |                                              |
| RR2    |0024h |0004h |Interrupt vectors                             |
|        |      |      |                                              |
| RR3    |0026h |0026h |Port A and B interrupt pending bits           |
|        |      |      |                                              |
| RR8    |0030h |0010h |Receive data buffer                           |
|        |      |      |                                              |
| RR10   |0034h |0014h |Miscellaneous status and parameters           |
|        |      |      |                                              |
| RR12   |0038h |0018h |Time constant low                             |
|        |      |      |                                              |
| RR13   |003Ah |001Ah |Time constant high                            |
|        |      |      |                                              |
| RR15   |003Eh |001Eh |External status control information           |
-----------------------------------------------------------------------

Baud Rate Constant Programming

8030 SCC write registers 12 and 13 contain the baud rate generator time constant values. If the baud rate generator is being used for clocking, the values in these registers determine the baud rate of the port. Write register 12 contains the low order byte of the time constant while write registers 13 contains the high order byte.

Note: To maintain compatibility with the Realtime Interface Co-Processor, application tasks should assume a PCLK frequency of 3.6864 Mhz, and use the SCCREGS PROM Service (INT A4h) when programming the SCC time constants. These PROM Services will adjust the time constants for the actual PCLK value on the specific co-processor adapter.

Calculating the Time Constant:

To calculate the time constant for async mode or FM synchronous mode, use the following formula:

      Time Constant = (3686400/(32 * Baud Rate)) - 2.
To calculate the time constant for NRZ or NRZI synchronous mode, the following formula is used:
      Time Constant = (3686400/(64 * Baud Rate)) - 2.
These formulas assume the digital phase-locked loop (DPLL) is used for the receive clock of the synchronous modes. If the DPLL is not used, use the following formula for Sync modes:
      Time Constant = (3686400/(2 * Baud Rate)) - 2.

Baud Rate Time Constants With Baud Rate Generator:

These constants are placed in write registers 12 and 13 (DPLL with Sync modes and divide by 16 with async modes) to achieve the desired baud rate.

            -----------------------------------------------------
            |    Async and FM Sync    | NRZ and NRZ1 Sync Mode  |
------------+-------------------------+-------------------------|
| Baud Rate | WR12  WR13  % Deviation | WR12  WR13  % Deviation |
|-----------+-------------------------+-------------------------|
|  19200    | 04h   00h       .01     | 01h   00h       .01     |
|   9600    | 0Ah   00h       .01     | 04h   00h       .01     |
|   7200    | 0Eh   00h       .01     | 06h   00h       .01     |
|   4800    | 16h   00h       .01     | 0Ah   00h       .01     |
|   3600    | 1Eh   00h       .01     | 0Eh   00h       .01     |
|   2400    | 2Eh   00h       .01     | 16h   00h       .01     |
|   2000    | 38h   00h       .70     | 1Bh   00h       .70     |
|   1800    | 3Eh   00h       .01     | 1Eh   00h       .01     |
|   1200    | 5Eh   00h       .01     | 2Eh   00h       .01     |
|    600    | BEh   00h       .01     | 5Eh   00h       .01     |
|    300    | 7Eh   01h       .01     | BEh   00h       .01     |
|    150    | FEh   02h       .01     | 7Eh   01h       .01     |
|    134.5  | 57h   03h       .06     | AAh   01h       .06     |
|    110    | 15h   04h       .03     | 0Ah   02h       .07     |
|     75    | FEh   05h       .01     | FEh   02h       .01     |
|     50    | FEh   08h       .01     | 7Eh   04h       .01     |
-----------------------------------------------------------------

The SCC, in conjunction with the co-processor adapter and electrical interface boards, has a complex clocking system. You are allowed to use any combination of programming and hardware options to achieve the desired clocking option. The only restriction on hardware is that two output lines cannot drive each other. Clocking interfaces to RTxC and TRxC are described in "Clocking and Timing".

8036 COUNTER/TIMER AND PARALLEL I/O UNIT (CIO)

Functions

The 8036 Counter/Timer and Parallel I/O Unit (CIO) provides peripheral I/O support through an integrated chip containing three independent 16-bit counters or timers, two independent 8-bit double-buffered I/O ports, and a special purpose 4-bit I/O port.

One timer and the 4-bit I/O port are used by the on-board watchdog timer to provide interrupt notification of a runaway CPU or a runaway operation.

Two timers and two ports are used in peripheral I/O control of data through the co-processor adapter's electrical interface boards.

The requirement for general peripheral I/O and timers is satisfied by the 8036 CIO. Features of this component are:

Microcode

Additional features of the 8036 CIO include microcode support for 8036 diagnostic routines and user interfaces for performing PROM Services.

These interfaces are defined in detail in "Diagnostic Test Modules" and "PROM Services," found on another diskette in this publication package.

Physical Characteristics

The hardware block diagram at the beginning of this chapter provides an overview of the interconnections.

8036 CIO Pin Functions

This section describes the pin functions for the 8036 CIO.

                  ------------------
            - <-->| AD7        PA7 |<--> -
            | <-->| AD6        PA6 |<--> |
   Address/ | <-->| AD5        PA5 |<--> |
   data bus | <-->| AD4        PA4 |<--> | Port A
            | <-->| AD3        PA3 |<--> |
            | <-->| AD2        PA2 |<--> |
            | <-->| AD1        PA1 |<--> |
            - <-->| AD0        PA0 |<--> -
 Bus timing - --->| AS         PC3 |<--> -
  and reset - --->| DS         PC2 |<--> | Port C
            - --->| R/W        PC1 |<--> |
    Control | --->| CS1        PC0 |<--> -
            - --->| CS0        PB7 |<--> -
            - <---| INT        PB6 |<--> |
            | --->| INTACK     PB5 |<--> |
  Interrupt | --->| IEI        PB4 |<--> | Port B
            - <---| IEO        PB3 |<--> |
                  |            PB2 |<--> |
                  |            PB1 |<--> |
                  |            PB0 |<--> -
                  ------------------
                    ^     ^     ^
                   +5V   GND   PCLK

CIO Port Assignments and Descriptions

One port and one timer of CIO-0 are used by the watchdog timer to provide interrupt notification of a runaway CPU. The remaining ports on the two CIOs are either used as modem controls for the serial ports or they are available for general purpose I/O with custom electrical interface boards. The remaining five timers are allocated to the user for application specific requirements.

The following tables show the bit assignments for CIO-0 and CIO-1 when using the 4-port RS-232-C, 8-port RS-232-C, and RS-232-C/RS-422-A interface boards.

                CIO-0 Bit Assignments

   ---------------------      ---------------------
   | Port A |  Signal  |      | Port B |  Signal  |
   |  Bit   |   Name   |      |  Bit   |   Name   |
   |--------+----------|      |--------+----------|
   |  PA0   |  DSR0    |      |  PB0   |  DSR1    |
   |  PA1   |  Unused  |      |  PB1   |  Unused  |
   |  PA2   |  HRS0    |      |  PB2   |  HRS1    |
   |  PA3   |  Unused  |      |  PB3   |  Unused  |
   |  PA4   |  RI0     |      |  PB4   |  RI1     |
   |  PA5   |  Unused  |      |  PB5   |  Unused  |
   |  PA6   |  DTR0    |      |  PB6   |  DTR1    |
   |  PA7   |  TxBLK0  |      |  PB7   |  TxBLK1  |
   ---------------------      ---------------------


                CIO-1 Bit Assignments

   ---------------------      ---------------------
   | Port A |  Signal  |      | Port B |  Signal  |
   |  Bit   |   Name   |      |  Bit   |   Name   |
   |--------+----------|      |--------+----------|
   |  PA0   |  RI2     |      |  PB0   |  TxBLK2  |
   |  PA1   |  RI3     |      |  PB1   |  TxBLK3  |
   |  PA2   |  RI4     |      |  PB2   |  TxBLK4  |
   |  PA3   |  RI5     |      |  PB3   |  TxBLK5  |
   |  PA4   |  RI6     |      |  PB4   |  TxBLK6  |
   |  PA5   |  RI7     |      |  PB5   |  TxBLK7  |
   |  PA6   |  Unused  |      |  PB6   |  Unused  |
   |  PA7   |  Unused  |      |  PB7   |  Unused  |
   ---------------------      ---------------------

   TxBLKX = 1   TxD disabled
   TxBLKX = 0   TxD enabled
Refer to "Watchdog Timer" for Port C pin assignments.

The following tables show the bit assignments for CIO-0 and CIO-1 when using the 8-port RS-422-A interface board.

                CIO-0 Bit Assignments

   ---------------------      ---------------------
   | Port A |  Signal  |      | Port B |  Signal  |
   |  Bit   |   Name   |      |  Bit   |   Name   |
   |--------+----------|      |--------+----------|
   |  PA0   |  Unused  |      |  PB0   |  Unused  |
   |  PA1   |  Unused  |      |  PB1   |  Unused  |
   |  PA2   |  Unused  |      |  PB2   |  Unused  |
   |  PA3   |  Unused  |      |  PB3   |  Unused  |
   |  PA4   |  Unused  |      |  PB4   |  Unused  |
   |  PA5   |  Unused  |      |  PB5   |  Unused  |
   |  PA6   |  Unused  |      |  PB6   |  Unused  |
   |  PA7   |  TxBLK0  |      |  PB7   |  TxBLK1  |
   ---------------------      ---------------------


                CIO-1 Bit Assignments

   ---------------------      ---------------------
   | Port A |  Signal  |      | Port B |  Signal  |
   |  Bit   |   Name   |      |  Bit   |   Name   |
   |--------+----------|      |--------+----------|
   |  PA0   |  Unused  |      |  PB0   |  TxBLK2  |
   |  PA1   |  Unused  |      |  PB1   |  TxBLK3  |
   |  PA2   |  Unused  |      |  PB2   |  TxBLK4  |
   |  PA3   |  Unused  |      |  PB3   |  TxBLK5  |
   |  PA4   |  Unused  |      |  PB4   |  TxBLK6  |
   |  PA5   |  Unused  |      |  PB5   |  TxBLK7  |
   |  PA6   |  Unused  |      |  PB6   |  Unused  |
   |  PA7   |  Unused  |      |  PB7   |  Unused  |
   ---------------------      ---------------------

   TxBLKX = 1   TxD disabled
   TxBLKX = 0   TxD enabled
Refer to "Watchdog Timer" for Port C pin assignments.

The following tables show the bit assignments for CIO-0 and CIO-1 when using the 6-port RS-232-C synchronous interface board.

                CIO-0 Bit Assignments

   ---------------------      ---------------------
   | Port A |  Signal  |      | Port B |  Signal  |
   |  Bit   |   Name   |      |  Bit   |   Name   |
   |--------+----------|      |--------+----------|
   |  PA0   |  DSR0    |      |  PB0   |  DSR1    |
   |  PA1   |  Unused  |      |  PB1   |  Unused  |
   |  PA2   |  HRS0    |      |  PB2   |  HRS1    |
   |  PA3   |  Unused  |      |  PB3   |  Unused  |
   |  PA4   |  RI0     |      |  PB4   |  RI1     |
   |  PA5   |  Unused  |      |  PB5   |  Unused  |
   |  PA6   |  DTR0    |      |  PB6   |  DTR1    |
   |  PA7   |  TxBLK0  |      |  PB7   |  TxBLK1  |
   ---------------------      ---------------------


                CIO-1 Bit Assignments

 ----------------- ------------------ ---------------------
 | Port A| Signal| | Port B| Signal | | Port C| Signal    |
 |  Bit  |  Name | |  Bit  |  Name  | |  Bit  |  Name     |
 |-------+-------| |-------+--------| |-------+-----------|
 |  PA0  |  RI2  | |  PB0  |  TxBLK2| |  PC0  |DTE/DCECLK2|
 |  PA1  |  RI3  | |  PB1  |  TxBLK3| |  PC1  |DTE/DCECLK3|
 |  PA2  |  RI4  | |  PB2  |  TxBLK4| |  PC2  |DTE/DCECLK4|
 |  PA3  |  RI5  | |  PB3  |  TxBLK5| |  PC3  |DTE/DCECLK5|
 |  PA4  |  HRS2 | |  PB4  |  DSR2  | ---------------------
 |  PA5  |  HRS3 | |  PB5  |  DSR3  |
 |  PA6  |  HRS4 | |  PB6  |  DSR4  |
 |  PA7  |  HRS5 | |  PB7  |  DSR5  |
 ----------------- ------------------

   TxBLKX = 1   TxD disabled
   TxBLKX = 0   TxD enabled
Refer to "Watchdog Timer" for Port C pin assignments.

Signal Pin Descriptions

--------------------------------------------------------------------
|Signal Name |Description                                          |
|------------+-----------------------------------------------------|
| DSR        | Data set ready                                      |
|            |                                                     |
| RI         | Ring indicate                                       |
|            |                                                     |
| HRS        | Half rate select (data rate selector)               |
|            |                                                     |
| N/A        | Not applicable                                      |
|            |                                                     |
| DTR        | Data terminal ready                                 |
|            |                                                     |
| TXBLKX     | Transmit block. When this bit is on, the 8030       |
|            |   SCC transmitter is blocked from the electrical    |
|            |   interface board so that data is not transferred.  |
|            |   While performing the local data wrap test, this   |
|            |   bit should be active (set to 1) to prevent data   |
|            |   from being transmitted.                           |
|            |                                                     |
| RxD        | Receive data                                        |
|            |                                                     |
| RxCLK      | Receive clock                                       |
--------------------------------------------------------------------

Clocking and Timing

The 8036 CIO peripheral clock (PCLK) has an operating frequency of 3.6864 Mhz.

The watchdog timer (timer 3) operates at a frequency of 900Hz (T3CLK). It has a range up to 72.81659 seconds in increments of about 1.11111 milliseconds. Refer to "Watchdog Timer".

Programming Considerations

Refer to the appropriate Zilog publication for a detailed description of the 8036 Counter/Timer and Parallel I/O Unit.

Programming the 8036 CIO is accomplished by loading the CIO control registers with the proper bits to implement the desired operation modes.

CIO counters/timers are treated as separate devices from the CIO ports. This allows greater flexibility in assigning timer resources.

Some of the 8036 CIO features are not used by the co-processor adapter. These include most notably the handshaking mode and its various options.

8036 CIO I/O Addresses and Registers

The base addresses of the CIOs are:

CIO-0 0180h
CIO-1 0500h

The 8036 operates in left shift mode. When performing I/O operations to the CIO, subsequent I/O operations must be separated by at least one CPU instruction. A good instruction to use is JMP $+2. This is required because the 80186 can process I/O operations faster than the CIO can handle them.

The addresses of individual registers are as shown in the following tables.

Main Control Registers:

Some of these registers are dedicated for Realtime Control Microcode use only and should not be directly written by applications. PROM Services provide needed support for application tasks.

-----------------------------------------------------------------
|I/O Address|      |                                            |
|-----------|Access|        Function                            |
|CIO-0|CIO-1|      |                                            |
|-----+-----+------+--------------------------------------------|
|0180h|0500h| R/W  |Master interrupt control register           |
|     |     |      |                                            |
|0182h|0502h| R/W  |Master configuration control register.      |
|     |     |      |  Bit 4 is dedicated to the watchdog timer  |
|     |     |      |  and should not be programmed.  Bit 3 (=0) |
|     |     |      |  allows ports A and B to operate           |
|     |     |      |  independently and should not be changed.  |
|     |     |      |                                            |
|0184h|0504h| R/W  |Port A interrupt vector                     |
|     |     |      |                                            |
|0186h|0506h| R/W  |Port B interrupt vector                     |
|     |     |      |                                            |
|0188h|0508h| R/W  |Counter/timer interrupt vector              |
|     |     |      |                                            |
|018Ah|050Ah| R/W  |Port C data path polarity register          |
|     |     |      |(Reserved for co-processor adapter use only)|
|     |     |      |                                            |
|018Ch|050Ch| R/W  |Port C Data Direction Register              |
|     |     |      |(Reserved for co-processor adapter use only)|
|     |     |      |                                            |
|018Eh|050Eh| R/W  |Port C Special I/O Control Register         |
|     |     |      |(Reserved for co-processor adapter use only)|
-----------------------------------------------------------------

Frequently Accessed Registers:

----------------------------------------------------------------
|I/O Address|      |                                           |
|-----------|Access|        Function                           |
|CIO-0|CIO-1|      |                                           |
|-----+-----+------+-------------------------------------------|
|0190h|0510h| R/W  |Port A command and status.  Bits 2-3 do not|
|     |     |      |  apply in the bit port mode.              |
|     |     |      |                                           |
|0192h|0512h| R/W  |Port B command and status.  Bits 2-3 do not|
|     |     |      |  apply in the bit port mode.              |
|     |     |      |                                           |
|0194h|0514h| R/W  |Counter/timer 1 command and status         |
|     |     |      |                                           |
|0196h|0516h| R/W  |Counter/timer 2 command and status         |
|     |     |      |                                           |
|0198h|0518h| R/W  |Counter/timer 3 command and status         |
|     |     |      |  (for Realtime Control Microcode use only)|
|     |     |      |                                           |
|019Ah|051Ah| R/W  |Port A data register                       |
|     |     |      |                                           |
|019Ch|051Ch| R/W  |Port B data register                       |
|     |     |      |                                           |
|019Eh|051Eh| R/W  |Port C data register                       |
|     |     |      | (for Realtime Control Microcode use only) |
----------------------------------------------------------------

Counter/Timer Registers:

-----------------------------------------------------------------
|I/O Address|      |                                            |
|-----------|Access|        Function                            |
|CIO-0|CIO-1|      |                                            |
|-----+-----+------+--------------------------------------------|
|01A0h|0520h|  R   |Counter/timer 1 current count MSB           |
|     |     |      |                                            |
|01A2h|0522h|  R   |Counter/timer 1 current count LSB           |
|     |     |      |                                            |
|01A4h|0524h|  R   |Counter/timer 2 current count MSB           |
|     |     |      |                                            |
|01A6h|0526h|  R   |Counter/timer 2 current count LSB           |
|     |     |      |                                            |
|01A8h|0528h|  R   |Counter/timer 3 current count MSB           |
|     |     |      |                                            |
|01AAh|052Ah|  R   |Counter/timer 3 current count LSB           |
|     |     |      |                                            |
|01ACh|052Ch| R/W  |Counter/timer 1 time constant MSB           |
|     |     |      |                                            |
|01AEh|052Eh| R/W  |Counter/timer 1 time constant LSB           |
|     |     |      |                                            |
|01B0h|0530h| R/W  |Counter/timer 2 time constant MSB           |
|     |     |      |                                            |
|01B2h|0532h| R/W  |Counter/timer 2 time constant MSB           |
|     |     |      |                                            |
|01B4h|0534h| R/W  |Counter/timer 3 time constant MSB           |
|     |     |      |  (for Realtime Control Microcode use only) |
|     |     |      |                                            |
|01B6h|0536h| R/W  |Counter/timer 3 time constant LSB           |
|     |     |      |  (for Realtime Control Microcode use only) |
|     |     |      |                                            |
|01B8h|0538h| R/W  |Counter/timer 1 Mode specification          |
|     |     |      |                                            |
|01BAh|053Ah| R/W  |Counter/timer 2 Mode specification          |
|     |     |      |                                            |
|01BCh|053Ch| R/W  |Counter/timer 3 Mode specification          |
|     |     |      |  (for Realtime Control Microcode use only) |
|     |     |      |                                            |
|01BEh|053Eh| R/W  |Current vector                              |
-----------------------------------------------------------------
Note:
MSB = Most significant byte
LSB = Least significant byte

Port A Specification Registers:

-----------------------------------------------------------------
|I/O Address|      |                                            |
|-----------|Access|        Function                            |
|CIO-0|CIO-1|      |                                            |
|-----+-----+------+--------------------------------------------|
|01C0h|0540h| R/W  |Port A mode specification.  Bits 3-7 must be|
|     |     |      |  zeros to keep the port specified as in bit|
|     |     |      |  port mode.  The de-skew timer function is |
|     |     |      |  not supported.  Therefore, bit 0 is for   |
|     |     |      |  latch on pattern match.                   |
|     |     |      |                                            |
|01C2h|0542h| R/W  |Port A handshake specification.  Register is|
|     |     |      |  always zero since handshaking is not used.|
|     |     |      |                                            |
|01C4h|0544h| R/W  |Port A data path polarity                   |
|     |     |      |                                            |
|01C6h|0546h| R/W  |Port A data direction (in or out/bit)       |
|     |     |      |                                            |
|01C8h|0548h| R/W  |Port A special I/O control (latches on a    |
|     |     |      |  transition)                               |
|     |     |      |                                            |
|01Cah|054Ah| R/W  |Port A pattern polarity                     |
|     |     |      |                                            |
|01CCh|054Ch| R/W  |Port A pattern transition (match or change) |
|     |     |      |                                            |
|01CEh|054Eh| R/W  |Port A pattern mask (which bits to test)    |
-----------------------------------------------------------------

Port B Specification Registers:

-----------------------------------------------------------------
|I/O Address|      |                                            |
|-----------|Access|        Function                            |
|CIO-0|CIO-1|      |                                            |
|-----+-----+------+--------------------------------------------|
|0100h|0550h| R/W  |Port B mode specification                   |
|     |     |      |                                            |
|0102h|0552h| R/W  |Port B handshake specification              |
|     |     |      |                                            |
|0104h|0554h| R/W  |Port B data path polarity                   |
|     |     |      |                                            |
|0106h|0556h| R/W  |Port B data direction                       |
|     |     |      |                                            |
|0108h|0558h| R/W  |Port B special I/O control                  |
|     |     |      |                                            |
|010Ah|055Ah| R/W  |Port B pattern polarity                     |
|     |     |      |                                            |
|010Ch|055Ch| R/W  |Port B pattern transition                   |
|     |     |      |                                            |
|01DEh|055Eh| R/W  |Port B pattern mask                         |
-----------------------------------------------------------------

Watchdog Timer

As a preventive device, a watchdog timer has been incorporated. This timer, once activated, must continually be strobed by software so that it will not time out. If the 80186 processor ever has a fatal error, this timer will reach its terminal count. The terminal count will:

The range for the watchdog timer is from 1.11111 msec to 72.81659 sec with a step size of 1.11111 msec.

The watchdog timer is timer 3 in CIO-0. The watchdog timer is shown below. Note that if the watch dog timer is never initialized, the LED will stay on.

----------------------------------------------------- -------------
| CIO-0 |     |        |                            | |   |   |   |
|Port C | Pin | Signal | Description                | |PC2|PC0|LED|
|-------+-----+--------+----------------------------| |---+---+---|
| PC0   | 19  | WDOG   | Timer 3 out, Watch Dog     | | 0 | 0 |On |
| PC1   | 20  | T3CLK  | Timer 3 clock input 900 Hz.| | 0 | 1 |On |
| PC2   | 21  | WD CNTL| Watchdog LED control       | | 1 | 0 |Off|
| PC3   | 22  | ED     | # of edges plugged into PC | | 1 | 1 |On |
----------------------------------------------------- -------------



           -----------     -----o Vcc
           |  CIO-0  |    ---
           | Timer-3 |    |R|              -------
           |         |    ---     -----    |     |   ---   Vcc
           |      PC0|------------| I |o---| AND |---|L|----o
  CLK -----|PC1   PC2|-------     -----  --|     |   ---
           -----------      -------------- -------
Note: Port C on CIO-1 can be programmed as desired by the user except when using the 6-port synchronous RS-232-C EIB.

SHARED STORAGE INTERFACE

Functions

The Shared Storage Interface Chip provides a convenient and flexible way of passing data and control bytes between the 80186 bus and the system unit bus. This is accomplished through an IBM CMOS gate array called the Shared Storage Interface Chip, an array of 10,000 gates. The VLSI gate array's basic purpose is to provide a high performance interface between the co-processor adapter and the system unit. All data communications between the system unit and the co-processor adapter are done through this interface. This is accomplished through the following functions performed by the Shared Storage Interface Chip:

Physical Characteristics

The Realtime Interface Co-Processor Multiport/2 is designed with 512K or 1M bytes of RAM storage. The system unit views this memory space in 8, 16, 32, or 64K-byte pages. Only one page is selected by the system unit at any given time. The page selector is a single-byte read/write I/O port register on the Shared Storage Interface Chip. Accessing this register from either the system unit or the Realtime Interface Co-Processor Multiport/2 maps Realtime Interface Co-Processor Multiport/2 RAM storage for the system unit.

Performance

Arbitration for the use of RAM is achieved by using a 25 Mhz clock. Each system unit request is sampled at different times by the clock. Thus, the clock "selects" the next CPU to utilize the RAM. Note that the system unit requests are generated from valid address, status, and command signals, while Realtime Interface Co-Processor Multiport/2 requests are generated from the status lines (S0, S1, S2) when they indicate a memory cycle or instruction fetch. All Realtime Interface Co-Processor Multiport/2 memory space should be programmed to accept the external ready signal.

Internally, all system unit reads and Realtime Interface Co-Processor Multiport/2 reads and writes are terminated early by the Shared Storage Interface Chip, and the RAM is made available to the other CPU. This is transparent to the CPUs. During a memory read, data is latched and made available to the CPU until the CPU's cycle is finished. During a memory write, because the CPU provides the data, once the RAM write cycle has been completed no further interaction with the CPU is needed. Thus, in both cases the Shared Storage Interface Chip can internally terminate the present CPU cycle and allow the other CPU to utilize the RAM. All this is done to increase the usage (bandwidth) of the RAM.

It is necessary to view the performance of the Shared Storage Interface Chip in terms of the RAM availability (or cycle time) to the system unit. The RAM cycle is 300 nanoseconds long. Thus, data can be accessed at 6.66 megabytes per second from the RAM. This does not imply that either of the processors can transfer this much data. It does mean that if both processors are utilizing RAM 100%, then the total rate of data being moved from/to the RAM could approach 6.66 megabytes per second.

The following table defines best-case cycle times and data rates for the RAM and CPUs. This assumes no contention when accessing RAM.

----------------------------------------------------------
| Device            | Cycle Time*   |Data Rate           |
|-------------------+---------------+--------------------|
| RAM               |  300.0 ns     |6.66 mbytes/sec     |
| Co-proc. adapter  |  542.5 ns     |3.69 mbytes/sec     |
| 80286 system unit |  500-600 ns** |3.33 - 4mbytes/sec  |
| 80386 system unit |  500-600 ns** |3.33 - 4mbytes/sec  |
----------------------------------------------------------
*  Does not include time lost due to refresh
** Since the system unit bus is asynchronous, this value can be
   500 or 600, depending on the degree of asynchronicity of any
   given cycle.

Under various conditions, the different CPUs exhibit different performance factors, never exceeding their maximum values. The following tables show the best-case and the worst-case wait states that can be expected.

----------------------------------------------------------------
|Device            |Normal      |Additional        |Total Cycle|
|(No Contention)   |Wait States |Wait States (Min) |Time (Min) |
|------------------+------------+------------------+-----------|
|Co-proc. adapter  |    0       |     0            |   542.5   |
|80286 system unit |    0       |     3 or 4       |  500-600  |
|80386 system unit |    0       |     3 or 4       |  500-600  |
----------------------------------------------------------------

----------------------------------------------------------------
|Device            |Normal      |Additional        |Total Cycle|
|(Contention)      |Wait States |Wait States (Max) |Time (Max) |
|------------------+------------+------------------+-----------|
|Co-proc. adapter  |    0       |      2           |    813.8  |
|80286 system unit |    0       |      9           |   1100.0  |
|80386 system unit |    0       |      9           |   1100.0  |
----------------------------------------------------------------

The Shared Storage Interface Chip is designed to provide maximum data throughput using a minimum amount of software on the system unit. Very little synchronous operation is required between the system unit and the Realtime Interface Co-Processor Multiport/2. This essentially asynchronous interface allows system unit applications to communicate directly with applications on the Realtime Interface Co-Processor Multiport/2 through shared storage space.

The Shared Storage Interface Chip has features that support maintenance and service. It monitors a watchdog timer and upon expiration, the Shared Storage Interface Chip subsequently interrupts both the system unit and the 80186 processor. Also, power-on diagnostics test basic functions and post error information to specific RAM locations.

During power-up sequences, the RAM storage is degated from the system unit to prevent the system unit from attempting execution of the RAM resident data that is mapped into the system unit RAM space.

All control, data, and address lines from the system unit, Realtime Interface Co-Processor Multiport/2, and RAM enter into the Shared Storage Interface Chip. Internally, the CPU signals are used to initiate memory cycles from or to the RAM. After the CPU is selected internally by the arbitration unit, the appropriate RAM signals are generated and data is transferred (except for a refresh, in which case there is no data involved). The arbitrator then deselects the CPU using the RAM and can then select the other CPU if it is waiting to use the RAM. Whenever the RAM is needed by both CPUs, one is selected and the other held in wait states. A wait state for a CPU is a variable integral number of CPU clocks.

A major feature of the Realtime Interface Co-Processor Multiport/2 is to relocate the memory and I/O space of the Realtime Interface Co-Processor Multiport/2 within the system unit memory and I/O space through a value programmed into internal registers of the Shared Storage Interface Chip. Due to limited space within the system unit memory map, the Realtime Interface Co-Processor Multiport/2 allows an 8, 16, 32, or 64K-byte "window" into the Realtime Interface Co-Processor Multiport/2 RAM. But the Realtime Interface Co-Processor Multiport/2 and Shared Storage Interface Chip can support up to 512K or 960K bytes of user RAM. Thus, the Shared Storage Interface Chip contains a register that allows the user to change this window to view different portions of RAM. The Realtime Interface Co-Processor Multiport/2 has access to all RAM and has no need to use paging.

Programming Considerations

Shared Storage Interface Chip Internal Register Summary

Within the Shared Storage Interface Chip several registers which regulate the communication between the Realtime Interface Co-Processor Multiport/2 and the system unit. The subsections that follow summarize the internal registers contained within the Shared Storage Interface Chip. Detailed register descriptions and bit definitions can be found in " Appendix A. Shared Storage Interface Chip Registers and Commands".

Register and Command Descriptions:

All registers are 8-bit read and/or write except for the SCCREG which is 16-bit read-only from the 80186.

COMREG
Command Register. COMREG is used to issue commands to reset, interrupt, and control the Realtime Interface Co-Processor Multiport/2.
CAD
Control Alternate Delete. CAD0, CAD1, CAD2 registers are used to search for a match of some specific address only accessed by the system unit after a "control alternate delete" sequence from the keyboard, which indicates a system restart to the Realtime Interface Co-Processor Multiport/2. When the address match is satisfied, the Shared Storage Interface Chip degates RAM.
CRDID
Identifies Realtime Interface Co-Processor Multiport/2 to the system unit.
CPUPG
CPU Page Register. CPUPG is used for page values by the system unit to access dynamic RAM on the Realtime Interface Co-Processor Multiport/2. A page is 8K, 16K, 32K, or 64K bytes long.
DREG
Data Register. DREG is a pseudo register used to access various registers pointed to by the PTRREG.
GAID
Used to identify which level of Shared Storage Interface Chip is installed.
ICAPAR
Parity Register for the Realtime Interface Co-Processor Multiport/2. ICAPAR0, ICAPAR1, ICARPAR2 are used to latch the address bus and status of the Realtime Interface Co-Processor during a RAM read access having a parity error.
IDAL
This is the DA6 register merged into the Shared Storage Interface Chip.
INITREG
Used to configure the Shared Storage Interface Chip.
LOCREG
Used to physically locate the Realtime Interface Co-Processor Multiport/2 memory space in the system unit memory map.
NMIMASK
Primarily used to mask the various Shared Storage Interface Chip internal NMIs available.
NMISTAT
Primarily used to report which NMI is active.
PCPAR
Used to latch the address bus and status of the system unit during a RAM read access having a parity error.
PTRREG
Used to point to and enable various other registers, which can then be accessed through the pseudo register, DREG.
SCCREG
Used to control communication options.
TREG
Used as a mailbox to pass data from the Realtime Interface Co-Processor Multiport/2 to the system unit. It is also involved in interrupt generation to the system unit.
GEOI
Used to clear the internal interrupt circuitry of the Shared Storage Interface Chip after INTCOM is executed by the system unit.
INITCOM
Used to interrupt the Realtime Interface Co-Processor Multiport/2.

Register Addresses and Initial Values:

-----------------------------------------------------------------
|                   |  POS     | PS/2     |Co-Proc.  |Power-Up  |
|                   |Address   |Address   |Adapter   | Value    |
| Register:         | (hex)    | (hex)    |Address   |(Note 3)  |
|                   |(Note 5)  |(Note 1)  | (hex)    |          |
|-------------------+----------+----------+----------+----------|
| COMREG            |   -      |   06     |   -      |0000 0000 |
| CAD0              |   -      |  (0C)    |   -      |0000 0000 |
| CAD1              |   -      |  (0D)    |   -      |0000 0000 |
| CAD2              |   -      |  (0E)    |   -      |0000 0000 |
| CPUPG             |   -      |   05     |  14      |UUUU UUUU |
| CRDIDL            |  00      |    -     |   -      |1111 0000 |
| CRDIDU            |  01      |    -     |   -      |1110 1111 |
| DREG              |   -      |   03     |   -      |UUUU UUUU |
| GAID              |   -      |  (0F)    |  18      |1100 0000 |
| ICAPAR0           |   -      |    -     |  0C      |0000 0000 |
| ICAPAR1           |   -      |    -     |  0E      |0000 0000 |
| ICAPAR2           |   -      |    -     |  10      |0000 0000 |
| IDAL              |   -      |    -     |  84      |0000 0000 |
| INITREG0 (Note 4) |  02      |  (12)    |  04      |0000 1000 |
| INITREG1          |   -      |  (10)    |  06      |0000 0000 |
| INITREG2 (Note 4) |   -      |  (08)    |   -      |0000 0000 |
| INITREG3          |  05      |  (13)    |  1A      |0000 0000 |
| LOCREG0           |  03      |   00     |  00      |UUUU UUUU |
| LOCREG1           |  04      |   01     |  02      |UUUU UUUU |
| NMIMASK           |   -      |    -     |  08      |0011 1111 |
| NMISTAT           |   -      |    -     |  0A      |0000 0000 |
| PCPAR0            |   -      |  (0A)    |  -       |0000 0000 |
| PCPAR1            |   -      |  (0B)    |  -       |0000 0000 |
| PCPAR2            |  05      |  (11)    |  -       |0000 0001 |
| PTRREG            |   -      |   02     |  -       |UUUU UUUU |
| SCCREG (Note 6)   |   -      |    -     | 880      |0000 0000 |
|                   |   -      |    -     |   -      |UOUO UOUO |
| TREG              |   -      |   04     |  12      |1111 1111 |
| GEOI (Note 2)     |   -      |    -     |  16      | N/A      |
| INTCOM (Note 2)   |   -      |  (09)    |   -      | N/A      |
-----------------------------------------------------------------
Notes:
  1. Values given in parenthesis are pointer register values. All other values are offsets and should be added to the base address value programmed in INITREG0.
  2. Default power-up values are not applicable.
  3. 0=logic level 0; 1=logic level 1. S=same or no change; U=undefined.
  4. INITREG2 is only three bits of INITREG0 and is system unit read-only, while INITREG0 is all eight bits and is read/write by both CPUs.
  5. POS address offsets are further encoded with a valid CARDEN.
  6. SCCREG is a 16-bit read-only register, read as 16-bit IORD at 880H.
Reset Conditions:
------------------------------------------------------------------
|                                               |Channel|Power-Up|
| Condition                                     | Reset | Reset  |
|-----------------------------------------------+-------+--------|
| PS/2 side of Multiport/2 RAM is deactivated.  |   X   |   X    |
| PS/2 side of Multiport/2 is in 'sleep' mode.  |   X   |   X    |
| Parity circuits are cleared.                  |   X   |   X    |
| CAD  is feature disabled.                     |       |   X    |
| Internal refresh counters and circuits are    |       |        |
|   cleared.                                    |       |   X    |
| Internal Multiport/2 interrupt circuits are   |       |        |
|   cleared.                                    |       |   X    |
| Internal PS/2 interrupt circuits are cleared. |   X   |   X    |
------------------------------------------------------------------

Memory Mapping

A major feature of the Realtime Interface Co-Processor Multiport/2 is to relocate the memory and I/O space of the co-processor adapter within the system unit memory and I/O space through a value programmed into internal registers of the Shared Storage Interface Chip.

Relocation and Paging Features:

The figure below shows the relocation feature as well as the paging feature. Due to limited space within the system unit memory map, the Realtime Interface Co-Processor Multiport/2 allows an 8K, 16K, 32K or 64K byte "window" into the co-processor adapter RAM. The window size is programmable and can be increased when system unit memory space is available. The Realtime Interface Co-Processor Multiport/2 and Shared Storage Interface Chip can support 960K bytes of RAM. Thus, the Shared Storage Interface Chip contains a register that allows the system unit program to change this window to view different portions of RAM. The Realtime Interface Co-Processor Multiport/2 has access to all RAM and has no need to use paging.

           PS/2 Memory Map               Multiport/2
           of Multiport/2                Memory Map
             (16M bytes)

              0FFFFFF hex                 0EFFFF hex
            |->-------<-|              |->-------<-|
            |  | XK  |  |              |  | XK  |  |
            |  |-----|  |              |  |-----|  |
            |  |  .  |  |              |  |  .  |  |
            |  |  .  |  |              |  |  .  |  |
            |  |  .  |  |              |  |  .  |  |
            |  |  .  |  |              |  |  .  |  |
            |  |  .  |  |              |  |  .  |  |
------------|->|-----|<-|--------------|->|-----|<-|-------------
|LOCREG'S|  |  | XK  |  |  |XK bytes|  |  | XK  |  |  |CPU pages|
----------  |  |-----|  |  ----------  |  |-----|  |  -----------
 (Maps      |  |  .  |  |  (Window;    |  |  .  |  |  (Selects
 co-proc.   |  |  .  |  |   XK=8K,     |  |  .  |  |   window)
 adapter    |  |  .  |  |   16K, 32K,  |  |  .  |  |
 RAM)       |  |  .  |  |   or 64K.    |  |  .  |  |
            |  |  .  |  |   Set by     |  |  .  |  |
            |->|-----|<-|   W1-4)      |->|-----|<-|
               | XK  |                    | XK  |
               -------                    -------
            0000000 hex                  000000 hex

I/O Relocation Feature:

The figure below portrays the movable I/O block feature. While the Realtime Interface Co-Processor Multiport/2 memory may be mapped on any boundary of the size of the window, the I/O is limited to a selection of 16 "slots" of eight I/O addresses each.

              PS/2 I/O Map
             of Multiport/2

                (16M bytes)
            |->--------- 3EA7 hex
            |  | 8 I/O |
            |  |-------| 3EA0 hex
            |  |   .   |
            |  |   .   |
            |  |   .   |
            |  |   .   |
            |  |   .   |
------------|->|-------| 00xx xx10 1010 0111 binary
|INITREG |  |  | 8 I/O |
----------  |  |-------| 00xx xx10 1010 0000 binary
 (Maps      |  |   .   |
 co-proc.   |  |   .   |
 adapter    |  |   .   |
 I/O)       |  |   .   |
            |  |   .   |
            |->|-------| 02A7 hex
               | 8 I/O |
               --------- 02A0 hex

Adapter Description File

Function

The Adapter Description File provides a software solution to a hardware problem for the Realtime Interface Co-Processor Multiport/2. The jumper and switch settings described in the Realtime Interface Co-Processor and Realtime Interface Co-Processor Multiport volumes are set by an Adapter Description File which controls the Programmable Option Select (POS) registers. The Guide to Operations for the Realtime Interface Co-Processor Multiport/2 includes an Adapter Description File diskette and instructions on its use. A menu of options regarding the following is included:

The options provided with the Adapter Description File are sufficient for most applications; however, if greater flexibility is required, please consult the following sections on how to set the POS registers through an Adapter Description File. Instructions on how to create an Adapter Description File can usually be found in the system unit Technical Reference.

POS Registers

The Realtime Interface Co-Processor Multiport/2 implements four registers to support the system unit POS. These four registers contain three bits that are set by the system unit and 27 bits that are set by the user. (All of these bits must be initialized for the co-processor adapter to function properly.) A description of how these registers relate to the Shared Storage Interface Chip registers follows.

-------------------------
|D7|D6|D5|D4|D3|D2|D1|D0|
-------------------------
 |  |  |  |  |  |  |  |  POS0 POS1 POS2 POS3  POS4       POS5
 |  |  |  |  |  |  |  |
 |  |  |  |  |  |  |  --- 0    1    SE  A13   A20        W1
 |  |  |  |  |  |  ------ 0    1    L1  A14   A21        W2
 |  |  |  |  |  --------- 0    1    L2  A15   A22        W4
 |  |  |  |  ------------ 0    1    L4  A16   A23        PLL/321
 |  |  |  --------------- 1    0    C1  A17   PLL/320    LOCAL1
 |  |  ------------------ 1    1    C2  A18   LOCAL0     DCE/DT
 |  --------------------- 1    1    C4  A19   DCE/DTE 0  CKS
 ------------------------ 1    1    C8  00    00         NCKI

POS0 and POS1

POS0 and POS1 form the ID for Realtime Interface Co-Processor Multiport/2, EFF0 hex. These bits are not controlled by the Adapter Description File. The system unit "SETUP" program uses this ID to identify that a Realtime Interface Co-Processor Multiport/2 is installed.

POS2

POS2 is INITREG0, but bits D0-3 are rotated to accommodate SE, which is architected at bit D0.

Sleep Enable (SE):

This bit is defined in the micro-channel to disable the attachment card from the system unit bus when cleared. It is cleared on a channel reset. This bit is normally only used by the system "SETUP" program. Users should only use with caution.

Interrupt Level (L1, L2, L4):

These bits determine the interrupt level that the co-processor adapter will operate on within the system unit environment.

Card Number (C1, C2, C4, C8):

These bits specify the system unit base I/O address for all I/O registers. Each card should have a unique address, compared with each other and any other attachment card in the system unit.

POS3

POS3 is LOCREG0. Bit D7 must be 0.

Address Bits (A13-19):

These bits indicate where the user desires the Realtime Interface Co-Processor Multiport/2 to be located within the system unit memory map. 16KB boundaries do not use A13. 32KB boundaries do not use A13-14. 64KB boundaries do not use A13-15. Values programmed into these bits for these various boundaries will be ignored. For safety, they should be programmed to "0" if not relevant.

Note: If the window size is changed dynamically, the user must keep track of where the boundary of the window has been moved. For example, if there is an 8K window initially at C200h segment (61h) and the size is changed to a 16K window, the new segment would be at C000h (60h).

POS4

POS4 (bits D0-3) is LOCREG1, plus three bits (D4-6) which map into the SCC register to control clocking options for port 0.

Address Bits (A20-23): These bits are a continuation of POS3. Program the value that corresponds to the desired location for the co-processor adapter with the system unit memory map.

PLL/32-0, LOCAL-0, DCE/DTE-0: These bits relate to SCC0 on the base card. See SCC section for more information.

POS5

POS5 (bits D0-2) is INITREG3. Bits D3-5 map into the SCC register to control clocking options for port 1. CKS (bit D6) is a bit architected by the micro-channel, but will always be set to one. The inversion of NCKI (bit D7) may be found in PCPAR2 as CKI.

Window Size (W1, W2, W4): This value selects the window size that the system unit views at any one time. 8KB is the default. All other values are reserved.

PLL/32-1, LOCAL-1, DCE/DTE-1: These bits relate to SCC1 on the base card. See SCC section for more information.

CHAPTER 3. ELECTRICAL INTERFACES

The Purpose of This Chapter

This chapter discusses those components which provide electrical interfaces between the Realtime Interface Co-Processor Multiport/2 and external devices. The components that are described are:

ELECTRICAL INTERFACE BOARDS

Functions

One pluggable electrical interface board is accommodated by each Realtime Interface Co-Processor Multiport/2 for converting TTL compatible signals to or from standard EIA or CCITT electrical signal compatibility and to provide the physical means for external communication. The five options provided are:

Other interfaces (such as V.35 and 20 mA current loop) are possible, including parallel interfaces, if interface boards are designed.

Clocking

Clocking is supported on the following interface boards:

All other ports have no clocking. See the SCC and Adapter Description File sections of "Chapter 2. Co-Processor Adapter Components" for programming information.

Physical Characteristics

The electrical interfaces include signals between the Realtime Interface Co-Processor Multiport/2 and the electrical interface board. The interface boards are modular boards, 6.0 inches x 3.5 inches x 0.75 inches in size, that mount onto the Realtime Interface Co-Processor Multiport/2 to provide an electrical interface to external devices that follow the RS-232-C or RS-422-A standards.

The SCCs for ports 0-3 of all the electrical interface boards are on the base card (SCC0 and SCC1). The SCC for ports 4-5 is resident on the electrical interface board for the 6-port RS-232-C electrical interface board. The SCCs for ports 4-7 are resident on the electrical interface boards (SCC2 and SCC3) for the 8-port RS-232-C, RS-232-C/RS-422-A boards, and the 8-port RS-422-A boards.

Interface Board Connectors

Each interface board (with the 78-pin "D" connector attached) connects electrically to the Realtime Interface Co-Processor Multiport/2 board through two 60-pin connector strips mounted on both boards. The interface board is physically secured to the base board by two sets of slotted stand-offs and one plastic stand-off.

            Electrical Interface Board Layout

    --------------------------------------------------
    |    ------------------------------------  ------|
  ------ |                                  |  |..|..|
--|    | |                                  |  |..|..|
| |78- | |                                  |  |..|..|   2X 60-pin
| |pin | |    SCCs, drivers, receivers,     |  |..|..|   connectors
| |con.| |     and discrete components      |  |..|..|  (K1 and K2)
| |K9B | |                                  |  |..|..|<--------
| |    | |                                  |  |..|..|
--|    | |                                  |  |..|..|
  ------ ------------------------------------  |..|..|
    --------------------------------------------------
                                                K2 K1



                           K2    K1
                         -------------
                         |02 01|02 01|
                         |04 03|04 03|
                         |06 05|06 05|
                         |08 07|08 07|
                         | .  .| .  .|
      Connector Strip    | .  .| .  .|
      Pin Designations   | .  .| .  .|
                         | .  .| .  .|
                         | .  .| .  .|
                         |     |     |
                         |56 55|56 55|
                         |58 57|58 57|
                         |60 59|60 59|
                         -------------

Electrical Interface Board IDs

Each board type is identified by an ID value on the board. The values designated for the different board types are:

Electrical Interface Type ID Value
4 or 8-port RS-232-C C7h
4/RS-232-C + 4/RS-422-A C8h
8-port RS-422-A BEh
6-port RS-232-C synchronous CFh
Reserved C0h -- FFh
Available for use 00h -- BDh, BFh

These ID values may be read from the electrical interface by using the diagnostic interface modules "Get Interface ID" and "Get Extended Interface ID." (Refer to "Diagnostic Test Modules," found on another diskette in this package.) The values are also available in the Interface Block (IB) at absolute locations 47Ah (Port A) and 47Bh (Port B). The IDCS (electrical interface card select) signal is available for selecting the electrical interface board to read the electrical interface board ID.

Electrical Interface Board - Parallel Interface

A parallel data bus is provided to the electrical interface board. RD1D4-7 is used for reading the electrical interface board id. Additional signals and the address lines are provided for further decoding, if necessary.

Connector Strip Pinouts

The signal descriptions of the two connector strips (K1 and K2) can be found in the following tables:

------------------------------------------------------------------
|            K1 Base/EIB Connector Descriptions                  |
|----------------------------------------------------------------|
|Connector |Signal      |Signal |Pin |I/O |Comments              |
|Pin       |Name        |Source |    |    |                      |
|----------+------------+-------+----+----+----------------------|
|K1-01     |AD0         |80186  |17  | B  |Pulled up on base     |
|K1-02     |-12V        |-----  |--  | -  |NC (No Connect)       |
|          |            |       |    |    |(8-port 422)          |
|K1-03     |AD1         |80186  |15  | B  |Pulled up on base     |
|K1-04     |AD2         |80186  |13  | B  |Pulled up on base     |
|K1-05     |AD3         |80186  |11  | B  |Pulled up on base     |
|K1-06     |AD4         |80186  |08  | B  |Pulled up on base     |
|K1-07     |AD5         |80186  |06  | B  |Pulled up on base     |
|K1-08     |AD6         |80186  |04  | B  |Pulled up on base     |
|K1-09     |+12V        |-----  |--  | -  |NC (8-port 422)       |
|K1-10     |AD7         |80186  |02  | B  |Pulled up on base     |
|K1-11     |SCC2CS      |SSTIC  |E07 | O  |Ports 4 and 5 Chip    |
|          |            |       |    |    |Select (8-port 422)   |
|K1-12     |SCC3CS      |SSTIC  |A01 | O  |Ports 6 and 7 Chip    |
|          |            |       |    |    |Select (8-port 422),  |
|          |            |       |    |    |NC (6-port 232)       |
|K1-13     |TXD0        |SCC0   |16  | O  |                      |
|K1-14     |RXD0        |SCC0   |14  | I  |NC (8-port 422)       |
|K1-15     |-RTS0       |SCC0   |20  | O  |NC (8-port 422)       |
|K1-16     |-12V        |-----  |--  | -  |NC (8-port 422)       |
|K1-17     |-CTS0       |SCC0   |21  | I  |NC (8-port 422)       |
|K1-18     |-DCD0       |SCC0   |22  | I  |NC (8-port 422)       |
|K1-19     |-RMTCLK10   |SCC0   |13  | I  |                      |
|K1-20     |-RMTCLK20   |SCC0   |15  | B  |                      |
|K1-21     |TXD1        |SCC0   |29  | O  |                      |
|K1-22     |RXD1        |SCC0   |31  | I  |                      |
|K1-23     |+12V        |-----  |--  | -  |NC (8-port 422)       |
|K1-24     |-RTS1       |SCC0   |26  | O  |NC (8-port 422)       |
|K1-25     |-CTS1       |SCC0   |25  | I  |NC (8-port 422)       |
|K1-26     |-DCD1       |SCC0   |24  | I  |NC (8-port 422)       |
|K1-27     |-RMTCLK11   |SCC0   |32  | I  |NC (8-port 422)       |
|K1-28     |-RMTCLK21   |SCC0   |30  | B  |NC (8-port 422)       |
|K1-29     |TXD2        |SCC1   |16  | O  |                      |
|K1-30     |RXD2        |SCC1   |14  | I  |                      |
|K1-31     |-RTS2       |SCC1   |20  | O  |NC (8-port 422)       |
|K1-32     |-CTS2       |SCC1   |21  | I  |NC (8-port 422)       |
|K1-33     |-DCD2       |SCC1   |22  | I  |NC (8-port 422)       |
|K1-34     |-RMTCLK12   |SCC1   |13  | I  |NC (8-port 422)       |
|K1-35     |-RMTCLK22   |SCC1   |15  | B  |NC (8-port 422)       |
|K1-36     |-DTR2       |SCC1   |19  | O  |NC (8-port 422)       |
|K1-37     |TXD3        |SCC1   |29  | O  |                      |
|K1-38     |RXD3        |SCC1   |31  | I  |                      |
|K1-39     |-RTS3       |SCC1   |26  | O  |NC (8-port 422)       |
|K1-40     |-CTS3       |SCC1   |25  | I  |NC (8-port 422)       |
|K1-41     |-DCD3       |SCC1   |24  | I  |NC (8-port 422)       |
|K1-42     |-RMTCLK13   |SCC1   |32  | I  |NC (8-port 422)       |
|K1-43     |-RMTCLK23   |SCC1   |30  | B  |NC (8-port 422)       |
|K1-44     |-DTR3       |SCC1   |27  | O  |NC (8-port 422)       |
|K1-45     |PA01        |CIO1   |37  | B  |NC (8-port 422)       |
|K1-46     |PA11        |CIO1   |36  | B  |NC (8-port 422)       |
|K1-47     |PA21        |CIO1   |35  | B  |NC (8-port 422)       |
|K1-48     |PA31        |CIO1   |34  | B  |NC (8-port 422)       |
|K1-49     |PA41        |CIO1   |33  | B  |NC (8-port 422)       |
|K1-50     |PA51        |CIO1   |32  | B  |NC (8-port 422)       |
|K1-51     |PA61        |CIO1   |31  | B  |NC (8-port 422)       |
|K1-52     |PA71        |CIO1   |30  | B  |NC (8-port 422)       |
|K1-53     |PB01        |CIO1   |10  | B  |                      |
|K1-54     |PB11        |CIO1   |11  | B  |                      |
|K1-55     |PB21        |CIO1   |12  | B  |                      |
|K1-56     |PB31        |CIO1   |13  | B  |                      |
|K1-57     |PB41        |CIO1   |14  | B  |                      |
|K1-58     |PB51        |CIO1   |15  | B  |                      |
|K1-59     |PB61        |CIO1   |16  | B  |NC (8-port 422)       |
|K1-60     |PB71        |CIO1   |17  | B  |NC (8-port 422)       |
------------------------------------------------------------------
------------------------------------------------------------------
|            K2 Base/EIB Connector Descriptions                  |
|----------------------------------------------------------------|
|Connector |Signal      |Signal |Pin |I/O |Comments              |
|Pin       |Name        |Source |    |    |                      |
|----------+------------+-------+----+----+----------------------|
|K2-01     |RDID86      |SSTIC  |K10 | O  |Card Select for EIB ID|
|K2-02     |RDID200     |SSTIC  |B09 | O  |NC (8-port 422)       |
|K2-03     |GND         |-----  |--  | -  |                      |
|K2-04     |RDID280     |SSTIC  |G10 | O  |NC (8-port 422)       |
|K2-05     |DTE/DCE CLK0|SSTIC  |L09 | O  |                      |
|K2-06     |+5V         |-----  |--  | -  |                      |
|K2-07     |PA00        |CIO0   |37  | B  |NC (8-port 422)       |
|K2-08     |PA10        |CIO0   |36  | B  |NC (8-port 422,       |
|          |            |       |    |    |6-port 232)           |
|K2-09     |GND         |-----  |--  | -  |                      |
|K2-10     |PA20        |CIO0   |35  | B  |NC (8-port 422)       |
|K2-11     |PA30        |CIO0   |34  | B  |NC (8-port 422,       |
|          |            |       |    |    |6-port 232)           |
|K2-12     |+5V         |-----  |--  | -  |                      |
|K2-13     |PA40        |CIO0   |33  | B  |NC (8-port 422)       |
|K2-14     |PA50        |CIO0   |32  | B  |NC (8-port 422,       |
|          |            |       |    |    |6-port 232)           |
|K2-15     |GND         |-----  |--  | -  |                      |
|K2-16     |PA60        |CIO0   |31  | B  |NC (8-port 422)       |
|K2-17     |PA70        |CIO0   |30  | B  |                      |
|K2-18     |+5V         |-----  |--  | -  |                      |
|K2-19     |PB00        |CIO0   |10  | B  |NC (8-port 422)       |
|K2-20     |PB10        |CIO0   |11  | B  |NC (8-port 422,       |
|          |            |       |    |    |6-port 232)           |
|K2-21     |GND         |-----  |--  | -  |                      |
|K2-22     |PB20        |CIO0   |12  | B  |NC (8-port 422)       |
|K2-23     |PB30        |CIO0   |13  | B  |NC (8-port 422,       |
|          |            |       |    |    |6-port 232)           |
|K2-24     |+5V         |-----  |--  | -  |                      |
|K2-25     |PB40        |CIO0   |14  | B  |NC (8-port 422)       |
|K2-26     |PB50        |CIO0   |15  | B  |NC (8-port 422,       |
|          |            |       |    |    |6-port 232)           |
|K2-27     |GND         |-----  |--  | -  |                      |
|K2-28     |PB60        |CIO0   |16  | B  |NC (8-port 422)       |
|K2-29     |PB70        |CIO0   |17  | B  |                      |
|K2-30     |+5V         |-----  |--  | -  |                      |
|K2-31     |-RD         |80186  |62  | O  |NC (8-port 422,       |
|          |            |       |    |    |6-port 232)           |
|K2-32     |CLKOUT      |80186  |56  | B  |                      |
|K2-33     |DTE/DCE CLK1|SSTIC  |K08 | O  |NC (8-port 422)       |
|K2-34     |-SCCINT     |SCC    |06  | I  |Pulled up on base     |
|K2-35     |-BINTAK     |SCC    |09  | O  |                      |
|K2-36     |GND         |-----  |--  | -  |                      |
|K2-37     |BR/-W       |SSTIC  |G05 | O  |Buffered              |
|K2-38     |-PCS0       |80186  |25  | O  |NC (8-port 422)       |
|K2-39     |-PCS2       |80186  |28  | O  |NC (8-port 422)       |
|K2-40     |ZIEOF       |CIO1   |20  | O  |                      |
|K2-41     |-BAS        |SSTIC  |H11 | O  |Buffered              |
|K2-42     |GND         |-----  |--  | -  |                      |
|K2-43     |-BDS        |SSTIC  |G04 | O  |Buffered              |
|K2-44     |-SYNC0      |SCC0   |12  | B  |NC (8-port 422,       |
|          |            |       |    |    |6-port 232)           |
|K2-45     |-SYNC1      |SCC0   |33  | O  |NC (8-port 422,       |
|          |            |       |    |    |6-port 232)           |
|K2-46     |-SYNC2      |SCC1   |12  | B  |NC (8-port 422,       |
|          |            |       |    |    |6-port 232)           |
|K2-47     |-SYNC3      |SCC1   |33  | B  |NC (8-port 422,       |
|          |            |       |    |    |6-port 232)           |
|K2-48     |GND         |-----  |--  | -  |                      |
|K2-49     |PC01        |CIO1   |21  | B  |NC (8-port 422)       |
|K2-50     |PC11        |CIO1   |22  | B  |NC (8-port 422)       |
|K2-51     |A0          |80186  |--  | O  |Latched AD0, NC 6-port|
|          |            |       |    |    |232                   |
|K2-52     |A1          |80186  |--  | O  |Latched AD1, NC 6-port|
|          |            |       |    |    |232                   |
|K2-53     |A2          |80186  |--  | O  |Latched AD2, NC 6-port|
|          |            |       |    |    |232                   |
|K2-54     |GND         |-----  |--  | -  |                      |
|K2-55     |A3          |80186  |--  | O  |Latched AD3, NC 6-port|
|          |            |       |    |    |232                   |
|K2-56     |A4          |80186  |--  | O  |Latched AD4, NC 6-port|
|          |            |       |    |    |232                   |
|K2-57     |-WR         |80186  |63  | O  |NC (8-port 422,       |
|          |            |       |    |    |6-port 232)           |
|K2-58     |PC21        |CIO1   |23  | B  |NC (8-port 422)       |
|K2-59     |PC31        |CIO1   |24  | B  |NC (8-port 422)       |
|K2-60     |GND         |-----  |--  | -  |                      |
------------------------------------------------------------------
Notes:
  1. TXBLK0-7 (PA70, PB70, PB01, PB11, PB21, PB31, PB41, and PB51)
  2. should be used to block the TXD of each SCC port. This is used
  3. during diagnostics to prevent data from being transmitted onto the line.
  4. DTR may be used for a control line or a DMA request line.
  5. RMTCLKx2-7 do not have the various options that RMTCLKx0-1 have, which are selectable by the SCCREG. The options are explained under the SCC section.

4- and 8-Port RS-232-C Electrical Interface Boards

The 4- and 8-port RS-232-C electrical interface boards conform with the standard EIA RS-232-C. The electrical interface board has circuitry necessary to convert from TTL logic levels to RS-232-C logic levels and vice versa for four or eight serial ports. The signals exit the electrical interface board through the 78-pin "D" connector.

Speed of Operation

The speed of operation of this interface is limited to a maximum of 19.2K bps on all RS-232-C ports. This co-processor adapter, however, supports speeds of up to 38.4K bps on ports 0 and 1.

Voltage Requirements

Voltage requirements are +5V, +12V, and -12V.

Electrical Interface Board ID

4- and 8-port RS-232-C electrical interface board type = C7h.

Connector Pin Descriptions

The following tables provide complete signal relationships between the SCC, the CIO, the 4-port or 8-port RS-232-C electrical interface boards, serial ports, and cables. RS-232-C interchange circuit designations are also provided. Ports 4-7 refer to the 8-port RS-232-C electrical interface board only.

-----------------------------------------------------------------
|    RS-232-C Port 0  (4-port or 8-port RS-232-C)               |
|---------------------------------------------------------------|
|Signal  |SCC/CIO |SCC/CIO  |TTL Conn.  |D-Shell|RS-232-C       |
| Name   |Source  |Pin/Name |Pin #      |  Pin  |Pin/Name       |
|--------+--------+---------+-----------+-------+---------------|
|TxD0    | SCC-0  |16/TXDA  |  K1-13    |  40   |02/BA - 103    |
|RxD0    | SCC-0  |14/RXDA  |  K1-14    |  02   |03/BB - 104    |
|RTS0    | SCC-0  |20/-RTSA |  K1-15    |  01   |04/CA - 105    |
|CTS0    | SCC-0  |21/-CTSA |  K1-17    |  61   |05/CB - 106    |
|DTECLK0 | SCC-0  |15/-TRXCA|  K1-20    |  41   |24/DA - 113    |
|SG      |  ---   |         |   ---     |  43   |07/AB - 102    |
|DCD0    | SCC-0  |22/-DCDA |  K1-18    |  22   |08/CF - 109    |
|RXCLKIN0| SCC-0  |13/-RTXCA|  K1-19    |  62   |17/DD - 115    |
|DTR0    | CIO-0  |31/PA-6  |  K2-16    |  60   |20/CD - 108.2  |
|DSR0    | CIO-0  |37/PA-0  |  K2-07    |  42   |06/CC - 107    |
|HRS0    | CIO-0  |35/PA-2  |  K2-10    |  21   |23/CH - 111    |
|RI0     | CIO-0  |33/PA-4  |  K2-13    |  03   |22/CE - 125    |
|TxCLKIN0| SCC-0  |15/-TRXCA|  K1-20    |  23   |15/DB - 114    |
-----------------------------------------------------------------

-----------------------------------------------------------------
|    RS-232-C Port 1  (4-port or 8-port RS-232-C)               |
|---------------------------------------------------------------|
|Signal  |SCC/CIO |SCC/CIO  |TTL Conn.  |D-Shell|RS-232-C       |
| Name   |Source  |Pin/Name |Pin #      |  Pin  |Pin/Name       |
|--------+--------+---------+-----------+-------+---------------|
|TxD1    | SCC-0  |29/TXDB  |  K1-21    |  04   |02/BA - 103    |
|RxD1    | SCC-0  |31/RXDB  |  K1-22    |  64   |03/BB - 104    |
|RTS1    | SCC-0  |26/-RTSB |  K1-24    |  63   |04/CA - 105    |
|CTS1    | SCC-0  |25/-CTSB |  K1-25    |  25   |05/CB - 106    |
|DTECLK1 | SCC-0  |30/-TRXCB|  K1-28    |  05   |24/DA - 113    |
|SG      |  ---   |         |   ---     |  07   |07/AB - 102    |
|DCD1    | SCC-0  |24/-DCDB |  K1-26    |  45   |08/CF - 109    |
|RXCLKIN1| SCC-0  |32/-RTXCB|  K1-27    |  26   |17/DD - 115    |
|DTR1    | CIO-0  |16/PB-6  |  K2-28    |  24   |20/CD - 108.2  |
|DSR1    | CIO-0  |10/PB-0  |  K2-19    |  06   |06/CC - 107    |
|HRS1    | CIO-0  |12/PB-2  |  K2-22    |  44   |23/CH - 111    |
|RI1     | CIO-0  |14/PB-4  |  K2-25    |  65   |22/CE - 125    |
|TxCLKIN1| SCC-0  |30/-TRXCB|  K1-28    |  46   |15/DB - 114    |
-----------------------------------------------------------------

-----------------------------------------------------------------
|    RS-232-C Port 2  (4-port or 8-port RS-232-C)               |
|---------------------------------------------------------------|
|Signal  |SCC/CIO |SCC/CIO  |TTL Conn.  |D-Shell|RS-232-C       |
| Name   |Source  |Pin/Name |Pin #      |  Pin  |Pin/Name       |
|--------+--------+---------+-----------+-------+---------------|
|TxD2    | SCC-1  |16/TXDA  |  K1-29    |  66   |02/BA - 103    |
|RxD2    | SCC-1  |14/RXDA  |  K1-30    |  28   |03/BB - 104    |
|RTS2    | SCC-1  |20/-RTSA |  K1-31    |  27   |04/CA - 105    |
|CTS2    | SCC-1  |21/-CTSA |  K1-32    |  48   |05/CB - 106    |
|SG      |  ---   |         |   ---     |  08   |07/AB - 102    |
|DCD2    | SCC-1  |22/-DCDA |  K1-33    |  09   |08/CF - 109    |
|DTR2    | SCC-1  |19/-DTRA |  K1-36    |  47   |20/CD - 108.2  |
|DSR2    | SCC-1  |12/-SYNCA|  K2-46    |  68   |06/CC - 107    |
|RI2     | CIO-1  |37/PA-0  |  K1-45    |  29   |22/CE - 125    |
-----------------------------------------------------------------

-----------------------------------------------------------------
|    RS-232-C Port 3  (4-port or 8-port RS-232-C)               |
|---------------------------------------------------------------|
|Signal  |SCC/CIO |SCC/CIO  |TTL Conn.  |D-Shell|RS-232-C       |
| Name   |Source  |Pin/Name |Pin #      |  Pin  |Pin/Name       |
|--------+--------+---------+-----------+-------+---------------|
|TxD3    | SCC-1  |29/TXDB  |  K1-37    |  69   |02/BA - 103    |
|RxD3    | SCC-1  |31/RXDB  |  K1-38    |  31   |03/BB - 104    |
|RTS3    | SCC-1  |26/-RTSB |  K1-39    |  30   |04/CA - 105    |
|CTS3    | SCC-1  |25/-CTSB |  K1-40    |  51   |05/CB - 106    |
|SG      |  ---   |         |   ---     |  67   |07/AB - 102    |
|DCD3    | SCC-1  |24/-DCDB |  K1-41    |  12   |08/CF - 109    |
|DTR3    | SCC-1  |27/-DTRB |  K1-44    |  50   |20/CD - 108.2  |
|DSR3    | SCC-1  |33/-SYNCB|  K2-47    |  71   |06/CC - 107    |
|RI3     | CIO-1  |36/PA-1  |  K1-46    |  32   |22/CE - 125    |
-----------------------------------------------------------------

-----------------------------------------------------------------
|    RS-232-C Port 4 (8-port RS-232-C)                          |
|---------------------------------------------------------------|
|Signal  |SCC/CIO |SCC/CIO  |TTL Conn.  |D-Shell|RS-232-C       |
| Name   |Source  |Pin/Name |Pin #      |  Pin  |Pin/Name       |
|--------+--------+---------+-----------+-------+---------------|
|TxD4    | SCC-2  |15/TXDA  |   ---     |  73   |02/BA - 103    |
|RxD4    | SCC-2  |13/RXDA  |   ---     |  54   |03/BB - 104    |
|RTS4    | SCC-2  |17/-RTSA |   ---     |  34   |04/CA - 105    |
|CTS4    | SCC-2  |18/-CTSA |   ---     |  15   |05/CB - 106    |
|SG      |  ---   |         |   ---     |  11   |07/AB - 102    |
|DCD4    | SCC-2  |19/-DCDA |   ---     |  74   |08/CF - 109    |
|DTR4    | SCC-2  |16/-DTRA |   ---     |  35   |20/CD - 108.2  |
|DSR4    | SCC-2  |11/-SYNCA|   ---     |  72   |06/CC - 107    |
|RI4     | CIO-1  |35/PA-2  |  K1-47    |  49   |22/CE - 125    |
-----------------------------------------------------------------

-----------------------------------------------------------------
|    RS-232-C Port 5 (8-port RS-232-C)                          |
|---------------------------------------------------------------|
|Signal  |SCC/CIO |SCC/CIO  |TTL Conn.  |D-Shell|RS-232-C       |
| Name   |Source  |Pin/Name |Pin #      |  Pin  |Pin/Name       |
|--------+--------+---------+-----------+-------+---------------|
|TxD5    | SCC-2  |25/TXDB  |   ---     |  55   |02/BA - 103    |
|RxD5    | SCC-2  |27/RXDB  |   ---     |  75   |03/BB - 104    |
|RTS5    | SCC-2  |23/-RTSB |   ---     |  16   |04/CA - 105    |
|CTS5    | SCC-2  |22/-CTSB |   ---     |  36   |05/CB - 106    |
|SG      |  ---   |         |   ---     |  70   |07/AB - 102    |
|DCD5    | SCC-2  |21/-DCDB |   ---     |  56   |08/CF - 109    |
|DTR5    | SCC-2  |24/-DTRB |   ---     |  17   |20/CD - 108.2  |
|DSR5    | SCC-2  |29/-SYNCB|   ---     |  33   |06/CC - 107    |
|RI5     | CIO-1  |34/PA-3  |  K1-48    |  52   |22/CE - 125    |
-----------------------------------------------------------------

-----------------------------------------------------------------
|    RS-232-C Port 6 (8-port RS-232-C)                          |
|---------------------------------------------------------------|
|Signal  |SCC/CIO |SCC/CIO  |TTL Conn.  |D-Shell|RS-232-C       |
| Name   |Source  |Pin/Name |Pin #      |  Pin  |Pin/Name       |
|--------+--------+---------+-----------+-------+---------------|
|TxD6    | SCC-3  |15/TXDA  |   ---     |  76   |02/BA - 103    |
|RxD6    | SCC-3  |13/RXDA  |   ---     |  57   |03/BB - 104    |
|RTS6    | SCC-3  |17/-RTSA |   ---     |  37   |04/CA - 105    |
|CTS6    | SCC-3  |18/-CTSA |   ---     |  18   |05/CB - 106    |
|SG      |  ---   |         |   ---     |  --   |07/AB - 102    |
|DCD6    | SCC-3  |19/-DCDA |   ---     |  77   |08/CF - 109    |
|DTR6    | SCC-3  |16/-DTRA |   ---     |  38   |20/CD - 108.2  |
|DSR6    | SCC-3  |11/-SYNCA|   ---     |  53   |06/CC - 107    |
|RI6     | CIO-1  |33/PA-4  |  K1-49    |  10   |22/CE - 125    |
-----------------------------------------------------------------

-----------------------------------------------------------------
|    RS-232-C Port 7 (8-port RS-232-C)                          |
|---------------------------------------------------------------|
|Signal  |SCC/CIO |SCC/CIO  |TTL Conn.  |D-Shell|RS-232-C       |
| Name   |Source  |Pin/Name |Pin #      |  Pin  |Pin/Name       |
|--------+--------+---------+-----------+-------+---------------|
|TxD7    | SCC-3  |25/TXDB  |   ---     |  58   |02/BA - 103    |
|RxD7    | SCC-3  |27/RXDB  |   ---     |  78   |03/BB - 104    |
|RTS7    | SCC-3  |23/-RTSB |   ---     |  19   |04/CA - 105    |
|CTS7    | SCC-3  |22/-CTSB |   ---     |  39   |05/CB - 106    |
|SG      |  ---   |         |   ---     |  --   |07/AB - 102    |
|DCD7    | SCC-3  |21/-DCDB |   ---     |  59   |08/CF - 109    |
|DTR7    | SCC-3  |24/-DTRB |   ---     |  20   |20/CD - 108.2  |
|DSR7    | SCC-3  |29/-SYNCB|   ---     |  14   |06/CC - 107    |
|RI7     | CIO-1  |32/PA-5  |  K1-50    |  13   |22/CE - 125    |
-----------------------------------------------------------------

6-Port RS-232-C Synchronous Electrical Interface Board

The 6-port synchronous RS-232-C electrical interface board conforms with the standard EIA RS-232-C. The electrical interface board has circuitry necessary to convert from TTL logic levels to RS-232-C logic levels and vice versa for six serial ports. The signals exit the electrical interface board through the 78-pin "D" connector.

Speed of Operation

The speed of operation of this interface is limited to a maximum of 19.2K bps on all RS-232-C ports. This co-processor adapter, however, supports speeds of up to 38.4K bps on ports 0 and 1.

Voltage Requirements

Voltage requirements are +5V, +12V, and -12V.

Electrical Interface Board ID

6-port RS-232-C synchronous electrical interface board type = CFh.

Connector Pin Descriptions

The following tables provide complete signal relationships between the SCC, the CIO, the 6-port RS-232-C synchronous electrical interface board, serial ports and cables. RS-232-C interchange circuit designations are also provided.

-----------------------------------------------------------------
|    RS-232-C Port 0 (6-Port RS-232-C Synchronous)              |
|---------------------------------------------------------------|
|Signal  |SCC/CIO |SCC/CIO  |TTL Conn.  |D-Shell|RS-232-C       |
| Name   |Source  |Pin/Name |Pin #      |  Pin  |Pin/Name       |
|--------+--------+---------+-----------+-------+---------------|
|TxD0    | SCC-0  |16/TXDA  |  K1-13    |  40   |02/BA - 103    |
|RxD0    | SCC-0  |14/RXDA  |  K1-14    |  02   |03/BB - 104    |
|RTS0    | SCC-0  |20/-RTSA |  K1-15    |  01   |04/CA - 105    |
|CTS0    | SCC-0  |21/-CTSA |  K1-17    |  61   |05/CB - 106    |
|DTECLK0 | SCC-0  |15/-TRXCA|  K1-20    |  41   |24/DA - 113    |
|SG      |  ---   |         |   ---     |  43   |07/AB - 102    |
|DCD0    | SCC-0  |22/-DCDA |  K1-18    |  22   |08/CF - 109    |
|RXCLKIN0| SCC-0  |13/-RTXCA|  K1-19    |  62   |17/DD - 115    |
|DTR0    | CIO-0  |31/PA-6  |  K2-16    |  60   |20/CD - 108.2  |
|DSR0    | CIO-0  |37/PA-0  |  K2-07    |  42   |06/CC - 107    |
|HRS0    | CIO-0  |35/PA-2  |  K2-10    |  21   |23/CH - 111    |
|RI0     | CIO-0  |33/PA-4  |  K2-13    |  03   |22/CE - 125    |
|TxCLKIN0| SCC-0  |15/-TRXCA|  K1-20    |  23   |15/DB - 114    |
-----------------------------------------------------------------

-----------------------------------------------------------------
|    RS-232-C Port 1 (6-Port RS-232-C Synchronous)              |
|---------------------------------------------------------------|
|Signal  |SCC/CIO |SCC/CIO  |TTL Conn.  |D-Shell|RS-232-C       |
| Name   |Source  |Pin/Name |Pin #      |  Pin  |Pin/Name       |
|--------+--------+---------+-----------+-------+---------------|
|TxD1    | SCC-0  |29/TXDB  |  K1-21    |  04   |02/BA - 103    |
|RxD1    | SCC-0  |31/RXDB  |  K1-22    |  64   |03/BB - 104    |
|RTS1    | SCC-0  |26/-RTSB |  K1-24    |  63   |04/CA - 105    |
|CTS1    | SCC-0  |25/-CTSB |  K1-25    |  25   |05/CB - 106    |
|DTECLK1 | SCC-0  |30/-TRXCB|  K1-28    |  05   |24/DA - 113    |
|SG      |  ---   |         |   ---     |  07   |07/AB - 102    |
|DCD1    | SCC-0  |24/-DCDB |  K1-26    |  45   |08/CF - 109    |
|RXCLKIN1| SCC-0  |32/-RTXCB|  K1-27    |  26   |17/DD - 115    |
|DTR1    | CIO-0  |16/PB-6  |  K2-28    |  24   |20/CD - 108.2  |
|DSR1    | CIO-0  |10/PB-0  |  K2-19    |  06   |06/CC - 107    |
|HRS1    | CIO-0  |12/PB-2  |  K2-22    |  44   |23/CH - 111    |
|RI1     | CIO-0  |14/PB-4  |  K2-25    |  65   |22/CE - 125    |
|TxCLKIN1| SCC-0  |30/-TRXCB|  K1-28    |  46   |15/DB - 114    |
-----------------------------------------------------------------

-----------------------------------------------------------------
|    RS-232-C Port 2 (6-Port RS-232-C Synchronous)              |
|---------------------------------------------------------------|
|Signal  |SCC/CIO |SCC/CIO  |TTL Conn.  |D-Shell|RS-232-C       |
| Name   |Source  |Pin/Name |Pin #      |  Pin  |Pin/Name       |
|--------+--------+---------+-----------+-------+---------------|
|TxD2    | SCC-1  |16/TXDA  |  K1-29    |  66   |02/BA - 103    |
|RxD2    | SCC-1  |14/RXDA  |  K1-30    |  28   |03/BB - 104    |
|RTS2    | SCC-1  |20/-RTSA |  K1-31    |  27   |04/CA - 105    |
|CTS2    | SCC-1  |21/-CTSA |  K1-32    |  48   |05/CB - 106    |
|DTECLK2 | SCC-1  |15/-TRXCA|  K1-35    |  19   |24/DA - 113    |
|SG      |  ---   |         |   ---     |  08   |07/AB - 102    |
|DCD2    | SCC-1  |22/-DCDA |  K1-33    |  09   |08/CF - 109    |
|RXCLKIN2| SCC-1  |13/-RTXCA|  K1-34    |  57   |17/DD - 115    |
|DTR2    | SCC-1  |19/-DTRA |  K1-36    |  47   |20/CD - 108.2  |
|DSR2    | CIO-1  |14/PB4   |  K1-57    |  68   |06/CC - 107    |
|HRS2    | CIO-1  |33/PA-4  |  K1-49    |  76   |23/CH - 111    |
|RI2     | CIO-1  |37/PA-0  |  K1-45    |  29   |22/CE - 125    |
|TXCLKIN2| SCC-1  |15/-TRXCA|  K1-35    |  78   |15/DD - 114    |
-----------------------------------------------------------------

-----------------------------------------------------------------
|    RS-232-C Port 3 (6-Port RS-232-C Synchronous)              |
|---------------------------------------------------------------|
|Signal  |SCC/CIO |SCC/CIO  |TTL Conn.  |D-Shell|RS-232-C       |
| Name   |Source  |Pin/Name |Pin #      |  Pin  |Pin/Name       |
|--------+--------+---------+-----------+-------+---------------|
|TxD3    | SCC-1  |29/TXDB  |  K1-37    |  69   |02/BA - 103    |
|RxD3    | SCC-1  |31/RXDB  |  K1-38    |  31   |03/BB - 104    |
|RTS3    | SCC-1  |26/-RTSB |  K1-39    |  30   |04/CA - 105    |
|CTS3    | SCC-1  |25/-CTSB |  K1-40    |  51   |05/CB - 106    |
|DTECLK3 | SCC-1  |30/-TRXCB|  K1-43    |  20   |24/DD - 113    |
|SG      |  ---   |         |   ---     |  67   |07/AB - 102    |
|DCD3    | SCC-1  |24/-DCDB |  K1-41    |  12   |08/CF - 109    |
|RXCLKIN3| SCC-1  |32/-RTXCB|  K1-42    |  77   |17/DD - 115    |
|DTR3    | SCC-1  |27/-DTRB |  K1-44    |  50   |20/CD - 108.2  |
|DSR3    | CIO-1  |15/-PB-5 |  K1-58    |  71   |06/CC - 107    |
|HRS3    | CIO-1  |32/-PA-5 |  K1-50    |  37   |23/CH - 111    |
|RI3     | CIO-1  |36/PA-1  |  K1-46    |  32   |22/CE - 125    |
|TXCLKIN3| SCC-1  |30/-TRXCB|  K1-43    |  59   |15/DB - 114    |
-----------------------------------------------------------------

-----------------------------------------------------------------
|    RS-232-C Port 4 (6-Port RS-232-C Synchronous)              |
|---------------------------------------------------------------|
|Signal  |SCC/CIO |SCC/CIO  |TTL Conn.  |D-Shell|RS-232-C       |
| Name   |Source  |Pin/Name |Pin #      |  Pin  |Pin/Name       |
|--------+--------+---------+-----------+-------+---------------|
|TxD4    | SCC-2  |15/TXDA  |   ---     |  73   |02/BA - 103    |
|RxD4    | SCC-2  |13/RXDA  |   ---     |  54   |03/BB - 104    |
|RTS4    | SCC-2  |17/-RTSA |   ---     |  34   |04/CA - 105    |
|CTS4    | SCC-2  |18/-CTSA |   ---     |  15   |05/CB - 106    |
|DTECLK4 | SCC-2  |14/-TRXCA|   ---     |  10   |24/DD - 113    |
|SG      |  ---   |         |   ---     |  11   |07/AB - 102    |
|DCD4    | SCC-2  |19/-DCDA |   ---     |  74   |08/CF - 109    |
|RXCLKIN4| SCC-2  |12/-RTXCA|   ---     |  18   |17/DD - 115    |
|DTR4    | SCC-2  |16/-DTRA |   ---     |  35   |20/CD - 108.2  |
|DSR4    | CIO-1  |16/PB-6  |  K1-59    |  72   |06/CC - 107    |
|HRS4    | CIO-1  |31/PA-6  |  K1-51    |  38   |23/CH - 111    |
|RI4     | CIO-1  |35/PA-2  |  K1-47    |  49   |22/CE - 125    |
|TXCLKIN4| SCC-2  |14/-TRXCA|   ---     |  39   |15/DB - 114    |
-----------------------------------------------------------------

-----------------------------------------------------------------
|    RS-232-C Port 5 (6-Port RS-232-C Synchronous)              |
|---------------------------------------------------------------|
|Signal  |SCC/CIO |SCC/CIO  |TTL Conn.  |D-Shell|RS-232-C       |
| Name   |Source  |Pin/Name |Pin #      |  Pin  |Pin/Name       |
|--------+--------+---------+-----------+-------+---------------|
|TxD5    | SCC-2  |25/TXDB  |   ---     |  55   |02/BA - 103    |
|RxD5    | SCC-2  |27/RXDB  |   ---     |  75   |03/BB - 104    |
|RTS5    | SCC-2  |23/-RTSB |   ---     |  16   |04/CA - 105    |
|CTS5    | SCC-2  |22/-CTSB |   ---     |  36   |05/CB - 106    |
|DTECLK5 | SCC-2  |26/-TRXCB|   ---     |  13   |24/DA - 113    |
|SG      |  ---   |         |   ---     |  70   |07/AB - 102    |
|DCD5    | SCC-2  |21/-DCDB |   ---     |  56   |08/CF - 109    |
|RXCLKIN | SCC-2  |28/-RTXCB|   ---     |  53   |17/DD - 115    |
|DTR5    | SCC-2  |24/-DTRB |   ---     |  17   |20/CD - 108.2  |
|DSR5    | CIO-1  |17/PB-7  |  K1-60    |  33   |06/CC - 107    |
|HRS5    | CIO-1  |30/PA-7  |  K1-52    |  58   |23/CH - 111    |
|RI5     | CIO-1  |34/PA-3  |  K1-48    |  52   |22/CE - 125    |
|TXCLKIN5| SCC-2  |26/-TRXCB|   ---     |  14   |15/DB - 114    |
-----------------------------------------------------------------

RS-232-C / RS-422-A Electrical Interface Board

The RS-232-C/RS-422-A electrical interface board conforms with the EIA and RS-232-C and RS-422-A standards. The RS-232-C/RS-422-A adapter card contains the signal conditioning circuitry to convert TTL logic levels to RS-232-C and RS-422-A logic levels and vice versa for four ports of each.

Speed of Operation

RS-232-C Ports:

The speed of operation of this interface is limited to a maximum of 19.2K bps on all RS-232-C ports. This co-processor adapter, however, supports speeds of up to 38.4K bps on ports 0 and 1.

RS-422-A Ports:

On this EIB, the speed of operation of this interface is limited to a maximum of 19.2K bps full duplex for each RS-422-A port although not necessarily simultaneously. RS-422-A can support up to ten devices per port. The maximum cable length of the interface cable is 1219 meters (4000 ft.).

Note: RS-422-A cables are not supported for outdoor operation.

Voltage Requirements

Voltage requirements are +5V, +12V, and -12V.

Lightning Protection

Lightning surge protection is provided on the RS-422-A adapters transmit and receive data lines by transorb components.

Electrical Interface Board ID

RS-232-C/RS-422-A electrical interface board type = C8h.

Connector Pin Descriptions

The following tables provide signal relationships between the SCC, the CIO, the RS-232-C/RS-422-A interface boards and serial ports. Input and output direction is given relative to the SCC and CIO.

-----------------------------------------------------------------
|    RS-232-C Port 0  (RS-232-C/RS-422-A)                       |
|---------------------------------------------------------------|
|Signal  |SCC/CIO |SCC/CIO  |TTL Conn.  |D-Shell|RS-232-C       |
| Name   |Source  |Pin/Name |Pin #      |  Pin  |Pin/Name       |
|--------+--------+---------+-----------+-------+---------------|
|TxD0    | SCC-0  |16/TXDA  |  K1-13    |  40   |02/BA - 103    |
|RxD0    | SCC-0  |14/RXDA  |  K1-14    |  02   |03/BB - 104    |
|RTS0    | SCC-0  |20/-RTSA |  K1-15    |  01   |04/CA - 105    |
|CTS0    | SCC-0  |21/-CTSA |  K1-17    |  61   |05/CB - 106    |
|DTECLK0 | SCC-0  |15/-TRXCA|  K1-20    |  41   |24/DA - 113    |
|SG      |  ---   |         |   ---     |  43   |07/AB - 102    |
|DCD0    | SCC-0  |22/-DCDA |  K1-18    |  22   |08/CF - 109    |
|RXCLKIN0| SCC-0  |13/-RTXCA|  K1-19    |  62   |17/DD - 115    |
|DTR0    | CIO-0  |31/PA-6  |  K2-16    |  60   |20/CD - 108.2  |
|DSR0    | CIO-0  |37/PA-0  |  K2-07    |  42   |06/CC - 107    |
|HRS0    | CIO-0  |35/PA-2  |  K2-10    |  21   |23/CH - 111    |
|RI0     | CIO-0  |33/PA-4  |  K2-13    |  03   |22/CE - 125    |
|TxCLKIN0| SCC-0  |15/-TRXCA|  K1-20    |  23   |15/DB - 114    |
-----------------------------------------------------------------

-----------------------------------------------------------------
|    RS-232-C Port 1  (RS-232-C/RS-422-A)                       |
|---------------------------------------------------------------|
|Signal  |SCC/CIO |SCC/CIO  |TTL Conn.  |D-Shell|RS-232-C       |
| Name   |Source  |Pin/Name |Pin #      |  Pin  |Pin/Name       |
|--------+--------+---------+-----------+-------+---------------|
|TxD1    | SCC-0  |29/TXDB  |  K1-21    |  04   |02/BA - 103    |
|RxD1    | SCC-0  |31/RXDB  |  K1-22    |  64   |03/BB - 104    |
|RTS1    | SCC-0  |26/-RTSB |  K1-24    |  63   |04/CA - 105    |
|CTS1    | SCC-0  |25/-CTSB |  K1-25    |  25   |05/CB - 106    |
|DTECLK1 | SCC-0  |30/-TRXCB|  K1-28    |  05   |24/DA - 113    |
|SG      |  ---   |         |   ---     |  07   |07/AB - 102    |
|DCD1    | SCC-0  |24/-DCDB |  K1-26    |  45   |08/CF - 109    |
|RXCLKIN1| SCC-0  |32/-RTXCB|  K1-27    |  26   |17/DD - 115    |
|DTR1    | CIO-0  |16/PB-6  |  K2-28    |  24   |20/CD - 108.2  |
|DSR1    | CIO-0  |10/PB-0  |  K2-19    |  06   |06/CC - 107    |
|HRS1    | CIO-0  |12/PB-2  |  K2-22    |  44   |23/CH - 111    |
|RI1     | CIO-0  |14/PB-4  |  K2-25    |  65   |22/CE - 125    |
|TxCLKIN1| SCC-0  |30/-TRXCB|  K1-28    |  46   |15/DB - 114    |
-----------------------------------------------------------------

-----------------------------------------------------------------
|    RS-232-C Port 2  (RS-232-C/RS-422-A)                       |
|---------------------------------------------------------------|
|Signal  |SCC/CIO |SCC/CIO  |TTL Conn.  |D-Shell|RS-232-C       |
| Name   |Source  |Pin/Name |Pin #      |  Pin  |Pin/Name       |
|--------+--------+---------+-----------+-------+---------------|
|TxD2    | SCC-1  |16/TXDA  |  K1-29    |  66   |02/BA - 103    |
|RxD2    | SCC-1  |14/RXDA  |  K1-30    |  28   |03/BB - 104    |
|RTS2    | SCC-1  |20/-RTSA |  K1-31    |  27   |04/CA - 105    |
|CTS2    | SCC-1  |21/-CTSA |  K1-32    |  48   |05/CB - 106    |
|SG      |  ---   |         |   ---     |  08   |07/AB - 102    |
|DCD2    | SCC-1  |22/-DCDA |  K1-33    |  09   |08/CF - 109    |
|DTR2    | SCC-1  |19/-DTRA |  K1-36    |  47   |20/CD - 108.2  |
|DSR2    | SCC-1  |12/-SYNCA|  K2-46    |  68   |06/CC - 107    |
|RI2     | CIO-1  |37/PA-0  |  K1-45    |  29   |22/CE - 125    |
-----------------------------------------------------------------

-----------------------------------------------------------------
|    RS-232-C Port 3  (RS-232-C/RS-422-A)                       |
|---------------------------------------------------------------|
|Signal  |SCC/CIO |SCC/CIO  |TTL Conn.  |D-Shell|RS-232-C       |
| Name   |Source  |Pin/Name |Pin #      |  Pin  |Pin/Name       |
|--------+--------+---------+-----------+-------+---------------|
|TxD3    | SCC-1  |29/TXDB  |  K1-37    |  69   |02/BA - 103    |
|RxD3    | SCC-1  |31/RXDB  |  K1-38    |  31   |03/BB - 104    |
|RTS3    | SCC-1  |26/-RTSB |  K1-39    |  30   |04/CA - 105    |
|CTS3    | SCC-1  |25/-CTSB |  K1-40    |  51   |05/CB - 106    |
|SG      |  ---   |         |   ---     |  67   |07/AB - 102    |
|DCD3    | SCC-1  |24/-DCDB |  K1-41    |  12   |08/CF - 109    |
|DTR3    | SCC-1  |27/-DTRB |  K1-44    |  50   |20/CD - 108.2  |
|DSR3    | SCC-1  |33/-SYNCB|  K2-47    |  71   |06/CC - 107    |
|RI3     | CIO-1  |36/PA-1  |  K1-46    |  32   |22/CE - 125    |
-----------------------------------------------------------------

------------------------------------------------------------------
|    RS-422-A Port 4  (RS-232-C/RS-422-A)                        |
|----------------------------------------------------------------|
|Signal |SCC/CIO| SCC/CIO |  TTL  |D-Con.|RS-422-A|Description   |
| Name  |Source | Pin/Name| Pin # |Pin # |25-Pin  |              |
|       |       |         |       |      |Conn.   |              |
|       |       |         |       |      |Pin/Name|              |
|-------+-------+---------+-------+------+--------+--------------|
|TxD4   | SCC-2 | 15/TXDA |  ---  | 73   |04/P4TXA|P4TXA         |
|       |       |         |       | 34   |02/P4TXB|P4TXB         |
|RxD4   | SCC-2 | 13/RXDA |  ---  | 54   |05/P4RXA|P4RXA         |
|       |       |         |       | 15   |03/P4RXB|P4RXB         |
|SG     |  ---  |         |  ---  | 11   |07/     |Signal ground |
|TxBLK4 | CIO-1 | 12/PB-2 | K1-55 |      |        |+RS-422 enable|
------------------------------------------------------------------

------------------------------------------------------------------
|    RS-422-A Port 5  (RS-232-C/RS-422-A)                        |
|----------------------------------------------------------------|
|Signal |SCC/CIO| SCC/CIO |  TTL  |D-Con.|RS-422-A|Description   |
| Name  |Source | Pin/Name| Pin # |Pin # |25-Pin  |              |
|       |       |         |       |      |Conn.   |              |
|       |       |         |       |      |Pin/Name|              |
|-------+-------+---------+-------+------+--------+--------------|
|TxD5   | SCC-2 | 25/TXDB |  ---  | 55   |04/P5TXA|P5TXA         |
|       |       |         |       | 16   |02/P5TXB|P5TXB         |
|RxD5   | SCC-2 | 27/RXDB |  ---  | 75   |05/P5RXA|P5RXA         |
|       |       |         |       | 36   |03/P5RXB|P5RXB         |
|SG     |  ---  |         |  ---  | 70   |07/     |Signal ground |
|TxBLK5 | CIO-1 | 13/PB-3 | K1-56 |      |        |+RS-422 enable|
------------------------------------------------------------------

------------------------------------------------------------------
|    RS-422-A Port 6  (RS-232-C/RS-422-A)                        |
|----------------------------------------------------------------|
|Signal |SCC/CIO| SCC/CIO |  TTL  |D-Con.|RS-422-A|Description   |
| Name  |Source | Pin/Name| Pin # |Pin # |25-Pin  |              |
|       |       |         |       |      |Conn.   |              |
|       |       |         |       |      |Pin/Name|              |
|-------+-------+---------+-------+------+--------+--------------|
|TXD6   | SCC-3 | 15/TXDA |  ---  | 76   |04/P6TXA|P6TXA         |
|       |       |         |       | 37   |02/P6TXB|P6TXB         |
|RXD6   | SCC-3 | 13/RXDA |  ---  | 57   |05/P6RXA|P6RXA         |
|       |       |         |       | 18   |03/P6RXB|P6RXB         |
|SG     |  ---  |         |  ---  | --   |07/     |Signal ground |
|TxBLK6 | CIO-1 | 14/PB-4 | K1-57 |      |        |+RS-422 enable|
------------------------------------------------------------------

------------------------------------------------------------------
|    RS-422-A Port 7  (RS-232-C/RS-422-A)                        |
|----------------------------------------------------------------|
|Signal |SCC/CIO| SCC/CIO |  TTL  |D-Con.|RS-422-A|Description   |
| Name  |Source | Pin/Name| Pin # |Pin # |25-Pin  |              |
|       |       |         |       |      |Conn.   |              |
|       |       |         |       |      |Pin/Name|              |
|-------+-------+---------+-------+------+--------+--------------|
|TxD7   | SCC-3 | 25/TXDB | DC-43 | 58   |04/P7TXA|P7TXA         |
|       |       |         |       | 19   |02/P7TXB|P7TXB         |
|RxD7   | SCC-3 | 27/RXDB | DC-12 | 78   |05/P7RXA|P7RXA         |
|       |       |         |       | 39   |03/P7RXB|P7TXB         |
|SG     |  ---  |         |  ---  | --   |07/     |Signal ground |
|TxBLK7 | CIO-1 | 15/PB-5 | K1-58 |      |        |+RS-422 enable|
------------------------------------------------------------------

8-Port RS-422-A Electrical Interface Board

The 8-port RS-422-A electrical interface board conforms with the EIA and RS-422-A standards. The 8-port RS-422-A adapter card contains the signal conditioning circuitry to convert TTL logic levels to RS-422-A logic levels and vice versa for eight serial ports.

Speed of Operation

RS-422-A Ports:

On this EIB, the speed of operation of this interface is limited to a maximum of 19.2K bps (ports 1-7) for each RS-422-A port (full duplex) not necessarily simultaneously. The co-processor adapter, however, supports speeds up to 64K bps on the first port. RS-422-A can support up to ten devices per port. The maximum cable length of the interface cable is 1219 meters (4000 ft.).

Note: RS-422-A cables are not supported for outdoor operation.

Voltage Requirements

Voltage requirement is +5V.

Lightning Protection

Lightning surge protection is provided on the RS-422-A adapters transmit and receive data lines by transorb components.

Electrical Interface Board ID

RS-422-A electrical interface board type = BEh.

Connector Pin Descriptions

The following tables provide signal relationships between the SCC, the CIO, the 8-port RS-422-A interface boards and serial ports. Input and output direction is given relative to the SCC and CIO.

-----------------------------------------------------------------
|    RS-422-A Port 0  (8-Port RS-422-A)                         |
|---------------------------------------------------------------|
|Signal |SCC/CIO| SCC/CIO  | TTL  |D-Con.|RS-422-A  |Description|
| Name  |Source | Pin/Name |Pin # |Pin # |25-Pin    |           |
|       |       |          |      |      |Conn.     |           |
|       |       |          |      |      |Pin/Name  |           |
|-------+-------+----------+------+------+----------+-----------|
|TxD0+  | SCC-0 | 16/TXDA  | K1-13|  40  |02/TXA    | POTXA     |
|TxD0-  |       |          |      |  01  |04/TXB    | POTXB     |
|RxD0+  | SCC-0 | 14/RXDA  | K1-14|  02  |03/RXA    | PORXA     |
|RxD0-  |       |          |      |  61  |05/RXB    | PORXB     |
|TxCLK0+| SCC-0 | 15/-TRXCA| K1-20|  21  |23/TXCLKA |           |
|TxCLK0-|       |          |      |  41  |24/TXCLKB |           |
|RxCLK0+| SCC-0 | 13/-RTXCA| K1-19|  03  |22/RXCLKA |           |
|RxCLK0-|       |          |      |  62  |17/RXCLKB |           |
|SG     |  ---  |          |  --- |  43  |07/       |           |
-----------------------------------------------------------------

-----------------------------------------------------------------
|    RS-422-A Port 1  (8-Port RS-422-A)                         |
|---------------------------------------------------------------|
|Signal |SCC/CIO| SCC/CIO |  TTL  |D-Con.|RS-422-A| Description |
| Name  |Source | Pin/Name| Pin # |Pin # |25-Pin  |             |
|       |       |         |       |      |Conn.   |             |
|       |       |         |       |      |Pin/Name|             |
|-------+-------+---------+-------+------+--------+-------------|
|TxD1+  | SCC-0 | 29/TXDB | K1-21 | 04   |02/TXA  | P1TXA       |
|TxD1-  |       |         |       | 63   |04/TXB  | P1TXB       |
|RxD1+  | SCC-0 | 31/RXDB | K1-22 | 64   |03/RXA  | P1RXA       |
|RxD1-  |       |         |       | 25   |05/RXB  | P1RXB       |
-----------------------------------------------------------------

-----------------------------------------------------------------
|    RS-422-A Port 2  (8-Port RS-422-A)                         |
|---------------------------------------------------------------|
|Signal |SCC/CIO| SCC/CIO |  TTL  |D-Con.|RS-422-A| Description |
| Name  |Source | Pin/Name| Pin # |Pin # |25-Pin  |             |
|       |       |         |       |      |Conn.   |             |
|       |       |         |       |      |Pin/Name|             |
|-------+-------+---------+-------+------+--------+-------------|
|TxD2+  | SCC-1 | 16/TXDA | K1-29 | 66   |02/TXA  | P2TXA       |
|TxD2-  |       |         |       | 27   |04/TXB  | P2TXB       |
|RxD2+  | SCC-1 | 14/RXDA | K1-30 | 28   |03/RXA  | P2RXA       |
|RxD2-  |       |         |       | 48   |05/RXB  | P2RXB       |
-----------------------------------------------------------------

-----------------------------------------------------------------
|    RS-422-A Port 3  (8-Port RS-422-A)                         |
|---------------------------------------------------------------|
|Signal |SCC/CIO| SCC/CIO |  TTL  |D-Con.|RS-422-A| Description |
| Name  |Source | Pin/Name| Pin # |Pin # |25-Pin  |             |
|       |       |         |       |      |Conn.   |             |
|       |       |         |       |      |Pin/Name|             |
|-------+-------+---------+-------+------+--------+-------------|
|TxD3+  | SCC-1 | 29/TXDB | K1-37 | 69   |02/TXA  | P3TXA       |
|TxD3-  |       |         |       | 30   |04/TXB  | P3TXB       |
|RxD3+  | SCC-1 | 31/RXDB | K1-38 | 31   |03/RXA  | P3RXA       |
|RxD3-  |       |         |       | 51   |05/RXB  | P3RXB       |
-----------------------------------------------------------------

-----------------------------------------------------------------
|    RS-422-A Port 4  (8-Port RS-422-A)                         |
|---------------------------------------------------------------|
|Signal |SCC/CIO| SCC/CIO |  TTL  |D-Con.|RS-422-A| Description |
| Name  |Source | Pin/Name| Pin # |Pin # |25-Pin  |             |
|       |       |         |       |      |Conn.   |             |
|       |       |         |       |      |Pin/Name|             |
|-------+-------+---------+-------+------+--------+-------------|
|TxD4+  | SCC-2 | 16/TXDA |  ---  | 73   |02/TXA  | P4TXA       |
|TxD4-  |       |         |  ---  | 34   |04/TXB  | P4TXB       |
|RxD4+  | SCC-2 | 14/RXDA |  ---  | 54   |03/RXA  | P4RXA       |
|RxD4-  |       |         |  ---  | 15   |05/RXB  | P4RXB       |
-----------------------------------------------------------------

-----------------------------------------------------------------
|    RS-422-A Port 5  (8-Port RS-422-A)                         |
|---------------------------------------------------------------|
|Signal |SCC/CIO| SCC/CIO |  TTL  |D-Con.|RS-422-A| Description |
| Name  |Source | Pin/Name| Pin # |Pin # |25-Pin  |             |
|       |       |         |       |      |Conn.   |             |
|       |       |         |       |      |Pin/Name|             |
|-------+-------+---------+-------+------+--------+-------------|
|TxD5+  | SCC-2 | 29/TXDB |  ---  | 55   |02/TXA  | P5TXA       |
|TxD5-  |       |         |  ---  | 16   |04/TXB  | P5TXB       |
|RxD5+  | SCC-2 | 31/RXDB |  ---  | 75   |03/RXA  | P5RXA       |
|RxD5-  |       |         |  ---  | 36   |05/RXB  | P5RXB       |
-----------------------------------------------------------------

-----------------------------------------------------------------
|    RS-422-A Port 6  (8-Port RS-422-A)                         |
|---------------------------------------------------------------|
|Signal |SCC/CIO| SCC/CIO |  TTL  |D-Con.|RS-422-A| Description |
| Name  |Source | Pin/Name| Pin # |Pin # |25-Pin  |             |
|       |       |         |       |      |Conn.   |             |
|       |       |         |       |      |Pin/Name|             |
|-------+-------+---------+-------+------+--------+-------------|
|TxD6+  | SCC-3 | 16/TXDA |  ---  | 76   |02/TXA  | P6TXA       |
|TxD6-  |       |         |  ---  | 37   |04/TXB  | P6TXB       |
|RxD6+  | SCC-3 | 14/RXDA |  ---  | 57   |03/RXA  | P6RXA       |
|RxD6-  |       |         |  ---  | 18   |05/RXB  | P6RXB       |
-----------------------------------------------------------------

-----------------------------------------------------------------
|    RS-422-A Port 7  (8-Port RS-422-A)                         |
|---------------------------------------------------------------|
|Signal |SCC/CIO| SCC/CIO |  TTL  |D-Con.|RS-422-A| Description |
| Name  |Source | Pin/Name| Pin # |Pin # |25-Pin  |             |
|       |       |         |       |      |Conn.   |             |
|       |       |         |       |      |Pin/Name|             |
|-------+-------+---------+-------+------+--------+-------------|
|TxD7+  | SCC-3 | 29/TXDB |  ---  | 58   |02/TXA  | P7TXA       |
|TxD7-  |       |         |  ---  | 19   |04/TXB  | P7TXB       |
|RxD7+  | SCC-3 | 31/RXDB |  ---  | 78   |03/RXA  | P7RXA       |
|RxD7-  |       |         |  ---  | 39   |05/RXB  | P7RXB       |
-----------------------------------------------------------------

LED INDICATOR

Functions

An LED (Light-Emitting Diode) indicator provides a visual status of the watchdog timer status and error status. The watchdog timer or error LED is illuminated when the watchdog timer expires or a hardware error is detected by microcode on the Realtime Interface Co-Processor Multiport/2. This LED powers-on in an "ON" state and is turned off after a successful power-on self-test (POST).

Physical Characteristics

The LED is located on the top of the Realtime Interface Co-Processor Multiport/2 and can be easily viewed with the system unit cover removed.

             Realtime Interface Co-Processor Multiport/2 Card Layout


                     ------ LED indicator
        -------------v------------------------------------------------------
        |O  ---------o  ------- ------------|||  -------   ------- ------  |
        |   | PROM  |---| CPU | |CIO ||SCC ||||  -------   ------- ---------
        |   |       |---|     | |----||----||||  -------           ------|
        |   ---------   ------- |CIO ||SCC ||||  -------           ------|
        |   --------------      ------------|||    ----- ----------      |
        |   --------------         ---------|||O   ----- | Gate   |------|
        |  ----------------------- |Bus DR ||||          | array  |------|
        |  |        DRAM         | ---------|||          |        |      |
        |O -----------------------          |||          ----------      ---
        ----------------------------------------   --            ----- O   |
                                             ^ -------------------   -------
                  Two 60-pin connectors ------
                     (K1 and K2)
The following states are indicated by the LED:
LED on = Watchdog timer expired, or microcode has detected a hardware error or power-on before completion of power-on self-test.
LED off = Normal operation under co-processor adapter

SYSTEM UNIT TO CO-PROCESSOR ADAPTER

The mechanical and electrical interface between the system unit and the Realtime Interface Co-Processor Multiport/2 consists of the I/O channel connectors on the system board in the system unit and the card edge tab connectors on the Realtime Interface Co-Processor Multiport/2.

      --------------------------------------------------------------------
      |O  ---------   ------- ------------|||  -------   ------- ------  |
      |   | PROM  |---| CPU | |CIO ||SCC ||||  -------   ------- ---------
      |   |       |---|     | |----||----||||  -------           ------|
      |   ---------   ------- |CIO ||SCC ||||  -------           ------|
      |   --------------      ------------|||    ----- ----------      |
      |   --------------         ---------|||O   ----- | Gate   |------|
      |  ----------------------- |Bus DR ||||          | array  |------|
      |  |        DRAM         | ---------|||          |        |      |
      |O -----------------------          |||          ----------      ---
      ----------------------------------------   --            ----- O   |
                                             -------------------   -------
                                               ^          ^  |
               Card edge tab connectors -------------------  |
                                                             |
                                                             |
                                                             |
                                                             |
               I/O channel connector -------------------     |
                                                       v     v
                                            ---------------------
    |              System board             |                   |
    |--------------------------------------------------------------
    |

COMMUNICATIONS PORTS

The 78-pin D-shell connector on the rear edge of the electrical interface boards is exposed at the rear of the system unit (see the diagram below). This connector provides the connection to all communications ports.

    ------------------------------------------------
    |    ----------------------------------  ------|
  ------ |                                |  |..|..|
--|    | |                                |  |..|..|
| |78- | |                                |  |..|..|   2X 60-pin
| |pin | |    SCCs, drivers, receivers,   |  |..|..|   connectors
| |con.| |     and discrete components    |  |..|..|  (K1 and K2)
| |K9B | |                                |  |..|..|<--------
| |    | |                                |  |..|..|
--|    | |                                |  |..|..|
  ------ ----------------------------------  |..|..|
    ------------------------------------------------
The following figure shows the pinout configuration of the 78-pin female communications connector (K9B) on the electrical interface board:
-------------------------------------------------------------------
\   20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01   /
 \   39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21    /
  \ 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 /
   \ 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60  /
    -----------------------------------------------------------

4 and 8-port RS-232-C, and RS-232-C/RS-422-A Ports 0-3

The following table defines the D-shell connector pin assignments for ports 0-3 for the 4-port RS-232-C, 8-port RS-232-C, and RS-232-C/RS-422-A electrical interface boards:

-----------------------------------------------------------
|    RS-232-C 78-Pin D-Shell Connector Pin Assignments    |
|---------------------------------------------------------|
| Signal  | Conn. K9B Ports | I/O |  Reset    | RS-232-C  |
| Name    | 0   1   2   3   |     |  Cond.    | Pin/Name  |
|---------+-----------------+-----+-----------+-----------|
| TxD     | 40  04  66  69  |  O  | Marking   | 02    BA  |
| RxD     | 02  64  28  31  |  I  | Undefined | 03    BB  |
| RTS     | 01  63  27  30  |  O  | Inactive  | 04    CA  |
| CTS     | 61  25  48  51  |  I  | Undefined | 05    CB  |
| DTECLK  | 41  05  --  --  |  O  | Inactive  | 24    DA  |
| SG      | 07  08  11  43  |  -  | --------  | 07    AB  |
| DCD     | 22  45  09  12  |  I  | Inactive  | 08    CF  |
| RxCLKIN | 62  26  --  --  |  I  | Undefined | 17    DD  |
| DTR     | 60  24  47  50  |  O  | Inactive  | 20    CD  |
| DSR     | 42  06  68  71  |  I  | Inactive  | 06    CC  |
| HRS     | 21  44  --  --  |  O  | Undefined | 23    CH  |
| RI      | 03  65  29  32  |  I  | Undefined | 22    CE  |
| TxCLKIN | 23  46  --  --  |  I  | Undefined | 15    DB  |
-----------------------------------------------------------

8-Port RS-232-C Electrical Interface Board Ports 4-7

The 8-port RS-232-C electrical interface board supports ports 4-7 in addition to those described for ports 0-3 in the previous section. The following table defines the D-shell connector pin assignments for those ports:

-----------------------------------------------------------
|    RS-232-C 78-Pin D-Shell Connector Pin Assignments    |
|---------------------------------------------------------|
| Signal  | Conn. K9B Ports | I/O |  Reset    | RS-232-C  |
| Name    | 4   5   6   7   |     |  Cond.    | Pin/Name  |
|---------+-----------------+-----+-----------+-----------|
| TxD     | 73  55  76  58  |  O  | Marking   | 02    BA  |
| RxD     | 54  75  57  78  |  I  | Undefined | 03    BB  |
| RTS     | 34  16  37  19  |  O  | Inactive  | 04    CA  |
| CTS     | 15  36  18  39  |  I  | Undefined | 05    CB  |
| DTECLK  | --  --  --  --  |  O  | Inactive  | 24    DA  |
| SG      | 67  70  67  70  |  -  | --------  | 07    AB  |
| DCD     | 74  56  77  59  |  I  | Inactive  | 08    CF  |
| RxCLKIN | --  --  --  --  |  I  | Undefined | 17    DD  |
| DTR     | 35  17  38  20  |  O  | Inactive  | 20    CD  |
| DSR     | 72  33  53  14  |  I  | Inactive  | 06    CC  |
| HRS     | --  --  --  --  |  O  | Undefined | 23    CH  |
| RI      | 49  52  10  13  |  I  | Undefined | 22    CE  |
| TxCLKIN | --  --          |  I  | Undefined | 15    DB  |
-----------------------------------------------------------

RS-232-C / RS-422-A Electrical Interface Board Ports 4-7

The RS-232-C/RS-422-A electrical interface board supports ports 4-7 in addition to those described for ports 0-3 in a previous section. The following table defines the D-shell connector pin assignments for those ports:

-----------------------------------------------------------
|    RS-422-A 78-Pin D-Shell Connector Pin Assignments    |
|---------------------------------------------------------|
| Signal  | Conn. K9B Ports | I/O |  Reset    | RS-422-A  |
| Name    | 4   5   6   7   |     |  Cond.    | 25-Pin    |
|         |                 |     |           | Conn.     |
|         |                 |     |           | Pin/Name  |
|---------+-----------------+-----+-----------+-----------|
| TxD     | 73  55  76  58  |  O  | Marking   | 02  P_TxA |
|         | 34  16  37  19  |     | Marking   | 04  P_TxB |
|         |                 |     |           |           |
| RxD     | 54  75  57  78  |  I  | Undefined | 03  P_RxA |
|         | 15  36  18  39  |     | Undefined | 05  P_RxB |
|         |                 |     |           |           |
| SG      | 67  70  67  70  |  -  | --------  | 07        |
-----------------------------------------------------------

6-Port Synchronous RS-232-C Electrical Interface Board

The following table defines the D-shell connector pin assignments for the 6-port RS-232-C electrical interface board:

------------------------------------------------------------------
|          6-Port Synchronous RS-232-C 78-Pin                    |
|          D-Shell Connector Pin Assignments                     |
|----------------------------------------------------------------|
| Signal  | Conn. K9B Ports       | I/O|   Reset    | RS-232-C   |
| Name    | 0   1   2   3   4   5 |    |   Cond.    | Pin/Name   |
|---------+-----------------------+----+------------+------------|
| TxD     | 40  04  66  69  73  55|  O |  Marking   | 02 - BA    |
| RxD     | 02  64  28  31  54  75|  I |  Undefined | 03 - BB    |
| RTS     | 01  63  27  30  34  16|  O |  Inactive  | 04 - CA    |
| CTS     | 61  25  48  51  15  36|  I |  Undefined | 05 - CB    |
| DTECLK  | 41  05  19  20  10  13|  O |  Inactive  | 24 - DA    |
| SG      | 43  07  08  67  11  70|  - |  --------  | 07 - AB    |
| DCD     | 22  45  09  12  74  56|  I |  Inactive  | 08 - CF    |
| RxCLKIN | 62  26  57  77  18  53|  I |  Undefined | 17 - DD    |
| DTR     | 60  24  47  50  35  17|  O |  Inactive  | 20 - CD    |
| DSR     | 42  06  68  71  72  33|  I |  Inactive  | 06 - CC    |
| HRS     | 21  44  76  37  38  58|  O |  Undefined | 23 - CH    |
| RI      | 03  65  29  32  49  52|  I |  Undefined | 22 - CE    |
| TxCLKIN | 23  46  78  59  39  14|  I |  Undefined | 15 - DB    |
------------------------------------------------------------------

8-Port EIA RS-422-A Electrical Interface Board Ports 0-3

The following table defines the D-shell connector pin assignments for ports 0-3 of the 8-port RS-422-A electrical interface board:

------------------------------------------------------------
|          8-Port EIA RS-422-A EIB D-Shell                 |
|          Connector Pin Assignments Ports 0-3             |
|----------------------------------------------------------|
| Signal| Conn. K9B Ports| I/O | Reset      | RS-422-A     |
|Name   | 0   1   2   3  |     | Cond.      | 25-Pin       |
|       |                |     |            |  Conn.       |
|       |                |     |            | Pin/Name     |
|-------+----------------+-----+------------+--------------|
|TxD+   | 40  04  66  69 | O   | Marking    | 02/TXA       |
|TxD-   | 01  63  27  30 |     | Marking    | 04/TXB       |
|TxCLK+ | 21  --  --  -- | I/O | Undefined  | 23/TxCLKA    |
|TxCLK- | 41  --  --  -- |     | Undefined  | 24/TxCLKB    |
|RxD+   | 02  64  28  31 | I   | Undefined  | 03/RxA       |
|RxD-   | 61  25  48  51 |     | Undefined  | 05/RxB       |
|RxCLK+ | 03  --  --  -- | I   | Undefined  | 22/RxCLKA    |
|RxCLK- | 62  --  --  -- |     | Undefined  | 17/RxCLKB    |
|GND    | 43  07  08  67 |     | --------   | 07/GND       |
------------------------------------------------------------

8-Port EIA RS-422-A Electrical Interface Board Ports 4-7

The following table defines the D-shell connector pin assignments for ports 4-7 of the 8-port RS-422-A electrical interface board:

------------------------------------------------------------
|   8-Port EIA RS-422-A EIB D-Shell                        |
|   Connector Pin Assignments Ports 4-7                    |
|----------------------------------------------------------|
| Signal| Conn. K9B Ports| I/O | Reset      | RS-422-A     |
|Name   | 4   5   6   7  |     | Cond.      | 25-Pin       |
|       |                |     |            |  Conn.       |
|       |                |     |            | Pin/Name     |
|-------+----------------+-----+------------+--------------|
|TxD+   | 73  55  76  58 | O   | Marking    | 02/TXA       |
|TxD-   | 34  16  37  19 |     | Marking    | 04/TXB       |
|TxCLK+ | --  --  --  -- | I/O | Undefined  | 23/TxCLKA    |
|TxCLK- | --  --  --  -- |     | Undefined  | 24/TxCLKB    |
|RxD+   | 54  75  57  78 | I   | Undefined  | 03/RxA       |
|RxD-   | 15  36  18  39 |     | Undefined  | 05/RxB       |
|RxCLK+ | --  --  --  -- | I   | Undefined  | 22/RxCLKA    |
|RxCLK- | --  --  --  -- |     | Undefined  | 17/RxCLKB    |
|GND    | 11  70  --  -- |     | --------   | 07/GND       |
------------------------------------------------------------

CHAPTER 4. EXTERNAL INTERFACES

This chapter discusses external interfaces, the third major grouping of hardware related to the Realtime Interface Co-Processor Multiport/2. The external interfaces that are described consist of:

MOLDED DISTRIBUTION BOX

Two molded distribution boxes are provided as options to the Realtime Interface Co-Processor Multiport/2:

8-Port Molded Distribution Box

The 8-port molded distribution box is available for use with the 8-port RS-232-C, 4-port RS-232-C, RS-232-C/RS-422-A, and 8-port RS-422-A interface boards.

The molded distribution box converts the 78-pin female D-shell connector (K9B) on a Realtime Interface Co-Processor Multiport/2 interface board to eight 25-pin male D-shell connectors.

The 8-port molded distribution box contains an eight-foot cable with a 78-pin male D-shell connector (K9A) to attach to the connector on a Realtime Interface Co-Processor Multiport/2 interface board, and a distribution box at the other end, containing the eight 25-pin male D-shell connectors (K00 - K07). The approximate dimensions of the distribution box are 9 inches in length, 3 inches in height, and 3 inches in depth.

-------     -------                          --------------------
|     --- ---     |                          |   Port 0 (K00)   |
|       | |       |                          |  --------------  |
| 78-pin| | 78-pin|------------------------|  \------------/  |
| female| |  male |------------------------|   Port 1 (K01)   |
| (K9B) | | (K9A) |      78-wire cable       |  --------------  |
|       | |       |        (8 feet)          |  \------------/  |
|     --- ---     |                          |   Port 2 (K02)   |
-------     -------                          |  --------------  |
 Rear of                                     |  \------------/  |
 co-processor                                |   Port 3 (K03)   |
 adapter                                     |  --------------  |
                                             |  \------------/  |
                                             |   Port 4 (K04)   |
                                             |  --------------  |
                                             |  \------------/  |
                                             |   Port 5 (K05)   |
       -----------------------------         |  --------------  |
 Pin 1 \ . . . . . . . . . . . . . / Pin 13  |  \------------/  |
 Pin 14 \ . . . . . . . . . . . . / Pin 25   |   Port 6 (K06)   |
         -------------------------           |  --------------  |
         25-pin D-shell connectors  -------->|  \------------/  |
                                             |   Port 7 (K07)   |
                                             |  --------------  |
                                             |  \------------/  |
                                             |                  |
                                             --------------------
The following table shows the connections from connector K9A to connectors K00 through K07:
-----------------------------------------------------------------
|              8-Port Molded Distribution Box                   |
|              K9A to K00 through K07 Connections               |
|---------------------------------------------------------------|
|K9A  Pin # ||K9A  Pin # ||K9A  Pin # ||K9A  Pin # ||K9A  Pin # |
|-----------++-----------++-----------++-----------++-----------|
|01   K00-04||17   K05-20||33   K05-06||49   K04-22||65   K01-22|
|02   K00-03||18   K06-05||34   K04-04||50   K03-20||66   K02-02|
|03   K00-22||19   K07-04||35   K04-20||51   K03-05||67   K04-07|
|04   K01-02||20   K07-20||36   K05-05||52   K05-22||67   K06-07|
|05   K01-24||21   K00-23||37   K06-04||53   K06-06||68   K02-06|
|06   K01-06||22   K00-08||38   K06-20||54   K04-03||69   K03-02|
|07   K00-07||23   K00-15||39   K07-05||55   K05-02||70   K05-07|
|08   K01-07||24   K01-20||40   K00-02||56   K05-08||70   K07-07|
|09   K02-08||25   K01-05||41   K00-24||57   K06-03||71   K03-06|
|10   K06-22||26   K01-17||42   K00-06||58   K07-02||72   K04-06|
|11   K02-07||27   K02-04||43   K13-07||59   K07-08||73   K04-02|
|12   K03-08||28   K02-03||44   K01-23||60   K00-20||74   K04-08|
|13   K07-22||29   K02-22||45   K01-08||61   K00-05||75   K05-03|
|14   K07-06||30   K03-04||46   K01-15||62   K00-17||76   K06-02|
|15   K04-05||31   K03-03||47   K02-20||63   K01-04||77   K06-08|
|16   K05-04||32   K03-22||48   K02-05||64   K01-03||78   K07-03|
-----------------------------------------------------------------

6-Port Molded Distribution Box

The 6-port molded distribution box is available for use with the 6-port RS-232-C interface board.

This molded distribution box converts the 78-pin female D-shell connector (K9B) on a Realtime Interface Co-Processor Multiport/2 interface board to six 25-pin male D-shell connectors.

The 6-port molded distribution box contains an eight-foot cable with a 78-pin male D-shell connector (K9A) to attach to the connector on a Realtime Interface Co-Processor Multiport/2 interface board, and a distribution box at the other end containing the six 25-pin male D-shell connectors (K00 - K05). The approximate dimensions of the distribution box are 9 inches in length, 3 inches in height, and 3 inches in depth.

-------     -------                           --------------------
|     --- ---     |                           |   Port 0 (K00)   |
|       | |       |                           |  --------------  |
| 78-pin| | 78-pin|-------------------------|  \------------/  |
| female| |  male |-------------------------|   Port 1 (K01)   |
| (K9B) | | (K9A) |      78-wire cable        |  --------------  |
|       | |       |        (8 feet)           |  \------------/  |
|     --- ---     |                           |   Port 2 (K02)   |
-------     -------                           |  --------------  |
 Rear of                                      |  \------------/  |
 co-processor adapter                         |   Port 3 (K03)   |
                                              |  --------------  |
       -----------------------------          |  \------------/  |
 Pin 1 \ . . . . . . . . . . . . . / Pin 13   |   Port 4 (K04)   |
 Pin 14 \ . . . . . . . . . . . . / Pin 25    |  --------------  |
         -------------------------            |  \------------/  |
         25-pin D-shell connectors  --------->|   Port 5 (K05)   |
                                              |  --------------  |
                                              |  \------------/  |
                                              --------------------
The following table shows the connections from connector K9A to connectors K00 through K05:
-----------------------------------------------------------------
|              6-Port Molded Distribution Box                   |
|              K9A to K00 through K05 Connections               |
|---------------------------------------------------------------|
|K9A  Pin # ||K9A  Pin # ||K9A  Pin # ||K9A  Pin # ||K9A  Pin # |
|-----------++-----------++-----------++-----------++-----------|
|01   K00-04||17   K05-20||33   K05-06||49   K04-22||65   K01-22|
|02   K00-03||18   K04-17||34   K04-04||50   K03-20||66   K02-02|
|03   K00-22||19   K02-24||35   K04-20||51   K03-05||67   K03-07|
|04   K01-02||20   K03-24||36   K05-05||52   K05-22||67   K03-07|
|05   K01-24||21   K00-23||37   K03-23||53   K05-17||68   K02-06|
|06   K01-06||22   K00-08||38   K04-23||54   K04-03||69   K03-02|
|07   K01-07||23   K00-15||39   K04-15||55   K05-02||70   K05-07|
|08   K02-07||24   K01-20||40   K00-02||56   K05-08||70   K05-07|
|09   K02-08||25   K01-05||41   K00-24||57   K02-17||71   K03-06|
|10   K04-24||26   K01-17||42   K00-06||58   K05-23||72   K04-06|
|11   K04-07||27   K02-24||43   K00-07||59   K03-15||73   K04-02|
|12   K03-08||28   K02-03||44   K01-23||60   K00-20||74   K04-08|
|13   K05-24||29   K02-22||45   K01-08||61   K00-05||75   K05-03|
|14   K05-15||30   K03-04||46   K01-15||62   K00-17||76   K02-23|
|15   K04-05||31   K03-03||47   K02-20||63   K01-04||77   K03-17|
|16   K05-04||32   K03-22||48   K02-05||64   K01-03||78   K02-15|
-----------------------------------------------------------------

RS-422-A Cabling

Cabling Recommendation

The following cabling recommendations apply for all cables that are to be constructed for use with this feature:

Correct operation of any interface depends on several factors that should be taken into consideration during installation. Installations in areas of high electrical noise should consider using shielded twisted pair cable to increase noise immunity, otherwise unshielded twisted pair wire is adequate. Using shielded twisted pair also helps eliminate interference from the Realtime Interface Co-Processor Multiport/2 and is strongly recommended. It is also recommended that metal D-shell connectors be used to terminate the shield and provide a low-impedance path to ground for noise. RS-422-A can support up to ten devices per line. The maximum length of the interface cable is 1219 meters (4000 feet).

Cable Characteristics

Typical physical characteristics for this cable are listed below. Consult cable manufacturer catalogs for further detailed information.

WRAP PLUGS

The second group of external interface components consists of the wrap plugs, which are described in this section. They are presented in the following subsections:

78-Pin D-Shell Connector Wrap Plug

A diagnostic wrap plug is provided with each of the Hardware Maintenance Libraries for diagnosing problems in the electrical interface boards as well as the Realtime Interface Co-Processor Multiport/2. One 78-pin wrap plug supports all 4-port and 8-port interface boards. The other 78-pin wrap plug supports the 6-port RS-232-C synchronous interface board. The 78-pin male wrap plugs are designed to wrap all signals (both RS-232-C and RS-422-A) at connector K9B. No cable is associated with these wrap plugs.

The following table shows all wrapped signal connections for the 78-pin wrap plug which supports all 4-port and 8-port interface boards:

------------------------------------------------------------------
|                78-Pin Wrap Plug for 4-port                     |
|                and 8-port Interface Boards                     |
|----------------------------------------------------------------|
|    | Connector  |       RS-232-C               |RS-422-A       |
|Port| K9B Pins   |       Signals Wrapped        |Signals Wrapped|
|----+------------+------------------------------+---------------|
|    |02 - 40     | TxD0 - RXD0                  |P0TXA - P0RXA  |
|    |01 - 61 - 22| RTS0 - CTS0 - DCD0           |P0TXB - P0RXB  |
| 0  |23 - 62 - 41| TXCLKIN0 - RXCLKIN0 - DTECLK0|P0TXCLKB -     |
|    |            |                              |      P0RXCLKB |
|    |03 - 21     | HRS0 - RI0                   |P0TXCLKA -     |
|    |            |                              |      P0RXCLKA |
|    |42 - 60     | DSR0 - DTR0                  |               |
|----+------------+------------------------------+---------------|
|    |04 - 64     | TxD1 - RXD1                  |P1TXA - P1RXA  |
|    |63 - 25 - 45| RTS1 - CTS1 - DCD1           |P1TXB - P1RXB  |
| 1  |46 - 26 - 05| TXCLKIN1 - RXCLKIN1 - DTECLK1|               |
|    |65 - 44     | HRS1 - RI1                   |               |
|    |06 - 24     | DSR1 - DTR1                  |               |
|----+------------+------------------------------+---------------|
|    |66 - 28     | TxD2 - RXD2                  |P2TXA - P2RXA  |
| 2  |27 - 48 - 09| RTS2 - CTS2 - DCD2           |P2TXB - P2RXB  |
|    |68 - 47 - 29| DSR2 - DTR2 - RI2            |               |
|----+------------+------------------------------+---------------|
|    |69 - 31     | TxD3 - RXD3                  |P3TXA - P3RXA  |
| 3  |30 - 51 - 12| RTS3 - CTS3 - DCD3           |P3TXB - P3RXB  |
|    |71 - 50 - 32| DSR3 - DTR3 - RI3            |               |
|----+------------+------------------------------+---------------|
|    |73 - 54     | TxD4 - RXD4                  |P4TXA - P4RXA  |
| 4  |34 - 15 - 74| RTS4 - CTS4 - DCD4           |P4TXB - P4RXB  |
|    |72 - 35 - 49| DSR4 - DTR4 - RI4            |               |
|----+------------+------------------------------+---------------|
|    |55 - 75     | TxD5 - RXD5                  |P5TXA - P5RXA  |
| 5  |16 - 36 - 56| RTS5 - CTS5 - DCD5           |P5TXB - P5RXB  |
|    |33 - 17 - 52| DSR5 - DTR5 - RI5            |               |
|----+------------+------------------------------+---------------|
|    |76 - 57     | TxD6 - RXD6                  |P6TXA - P6RXA  |
| 6  |37 - 18 - 77| RTS6 - CTS6 - DCD6           |P6TXB - P6RXB  |
|    |53 - 38 - 10| DSR6 - DTR6 - RI6            |               |
|----+------------+------------------------------+---------------|
|    |58 - 78     | TxD7 - RXD7                  |P7TXA - P7RXA  |
| 7  |19 - 39 - 59| RTS7 - CTS7 - DCD7           |P7TXB - P7RXB  |
|    |14 - 20 - 13| DSR7 - DTR7 - RI7            |               |
------------------------------------------------------------------
The following table shows all wrapped signal connections for the 78-pin wrap plug which supports the 6-port RS-232-C synchronous interface board:
---------------------------------------------------
|           78-Pin Wrap Plug for 6-port           |
|           RS-232-C Interface Board              |
|-------------------------------------------------|
|    | Connector  |       RS-232-C                |
|Port| K9B Pins   |       Signals Wrapped         |
|----+------------+-------------------------------|
|    |02 - 40     | TxD0 - RXD0                   |
|    |01 - 61 - 22| RTS0 - CTS0 - DCD0            |
| 0  |23 - 62 - 41| TXCLKIN0 - RXCLKIN0 - TXCLK0  |
|    |03 - 21     | HRS0 - RI0                    |
|    |42 - 60     | DSR0 - DTR0                   |
|----+------------+-------------------------------|
|    |04 - 64     | TxD1 - RXD1                   |
|    |63 - 25 - 45| RTS1 - CTS1 - DCD1            |
| 1  |46 - 26 - 05| TXCLKIN1 - RXCLKIN1 - TXCLK1  |
|    |44 - 65     | HRS1 - RI1                    |
|    |06 - 24     | DSR1 - DTR1                   |
|----+------------+-------------------------------|
|    |66 - 28     | TxD2 - RXD2                   |
|    |27 - 48 - 09| RTS2 - CTS2 - DCD2            |
| 2  |78 - 57 - 19| TXCLKIN2 - RXCLKIN2 - TXCLK2  |
|    |76 - 29     | HRS2 - RI2                    |
|    |68 - 47     | DSR2 - DTR2                   |
|----+------------+-------------------------------|
|    |69 - 31     | TxD3 - RXD3                   |
|    |30 - 51 - 12| RTS3 - CTS3 - DCD3            |
| 3  |59 - 77 - 20| TXCLKIN3 - RXCLKIN3 - TXCLK3  |
|    |37 - 32     | HRS3 - RI3                    |
|    |71 - 50     | DSR3 - DTR3                   |
|----+------------+-------------------------------|
|    |73 - 54     | TxD4 - RXD4                   |
|    |34 - 15 - 74| RTS4 - CTS4 - DCD4            |
| 4  |39 - 18 - 10| TXCLKIN4 - RXCLKIN4 - TXCLK4  |
|    |38 - 49     | HRS4 - RI4                    |
|    |72 - 35     | DSR4 - DTR4                   |
|----+------------+-------------------------------|
|    |55 - 75     | TxD5 - RXD5                   |
|    |16 - 36 - 56| RTS5 - CTS5 - DCD5            |
| 5  |14 - 53 - 13| TXCLKIN5 - RXCLKIN5 - TXCLK5  |
|    |58 - 52     | HRS5 - RI5                    |
|    |33 - 17     | DSR5 - DTR5                   |
---------------------------------------------------

Molded Distribution Box Wrap Plug

Two female wrap plugs are provided with each 8-port molded distribution box for diagnosing problems in the co-processor adapter, the electrical interface boards, or the molded distribution box. One wrap plug (P/N 09F1799) is used for ports 0 and 1; the other wrap plug (P/N 6425494) is used for ports 2 through 7.

The signals that are wrapped within the wrap plugs are shown below. The wrap connection is made from each transmit output signal and looped back to the corresponding receive input signal on the 25-pin D-shell connector.

Note: Each of the wrap plugs is used for both RS-232-C and RS-422-A.

------------------------------------------------
|      Wrap Connections for Ports 0 and 1      |
|----------------------------------------------|
|  RS-232-C Signals Wrapped  | Associated Pins |
|----------------------------+-----------------|
|  TXD - RXD                 | 02 - 03         |
|  RTS - CTS - DCD           | 04 - 05 - 08    |
|  HRS - RI                  | 23 - 22         |
|  DTR - DSR                 | 20 - 06         |
------------------------------------------------

------------------------------------------------
|      Wrap Connections for Ports 0 and 1      |
|----------------------------------------------|
|  RS-422-A Signals Wrapped  | Associated Pins |
|----------------------------+-----------------|
|  TXA - RXA                 | 02 - 03         |
|  TXB - RXB                 | 04 - 05         |
------------------------------------------------

------------------------------------------------
|    Wrap Connections for Ports 2 through 7    |
|----------------------------------------------|
|  RS-232-C Signals Wrapped  | Associated Pins |
|----------------------------+-----------------|
|  TXD - RXD                 | 02 - 03         |
|  RTS - CTS - DCD           | 04 - 05 - 08    |
|  DTR - DSR - RI            | 20 - 06 - 22    |
------------------------------------------------

------------------------------------------------
|    Wrap Connections for Ports 2 through 7    |
|----------------------------------------------|
|  RS-422-A Signals Wrapped  | Associated Pins |
|----------------------------+-----------------|
|  TXA - RXA                 | 04 - 05         |
|  TXB - RXB                 | 02 - 03         |
------------------------------------------------
A single female wrap plug is provided with each 6-port molded distribution box for diagnosing problems in the co-processor adapter, the electrical interface board, or the molded distribution box. The same wrap plug (P/N 33F8968) is used for all ports (0 thru 5).

The signals that are wrapped within the wrap plug are shown below. The wrap connection is made from each transmit output signal and looped back to the corresponding receive input signal on the 25-pin D-shell connector.

------------------------------------------------
|      Wrap Connections for Ports 0 thru 5     |
|----------------------------------------------|
|  RS-232-C Signals Wrapped  | Associated Pins |
|----------------------------+-----------------|
|  TXD - RXD                 | 02 - 03         |
|  RTS - CTS - DCD           | 04 - 05 - 08    |
|  HRS - RI                  | 23 - 22         |
|  DTR - DSR                 | 20 - 06         |
|  TXCLK - RXCLK - TXCLKIN   | 24 - 17 - 15    |
------------------------------------------------

APPENDIX A. SHARED STORAGE INTERFACE CHIP REGISTERS AND COMMANDS

This appendix describes the registers contained within the Shared Storage Interface Chip and the commands associated with it.

SHARED STORAGE INTERFACE CHIP REGISTERS

This section describes in detail the registers contained within the Shared Storage Interface Chip.

Bits are described with bit zero being the least significant bit. Bits which are designated with "U" take on an undefined or unpredictable state after power-up or reset commands. Bits which are designated with "S" take on the same state as before the reset command.

The "base address" referenced on the following pages is explained under "Initialization Registers (INITREG0, 1, 2, 3)".

Command Register (COMREG)

Description: The COMREG is a system unit read/write register. Its purpose is to provide control over the Co-Processor Adapter from the system unit.

I/O Addresses:

   System Unit - COMREG = Base Address +0006h
   Co-Processor Adapter - None (See NMIMASK and NMISTAT registers)
Register Format:
                -------------------------
                |D7|D6|D5|D4|D3|D2|D1|D0|
                -------------------------
                 |  |  |  |  |  |  |  |
                 |  |  |  |  |  |  |  --- RC - Reset Command
                 |  |  |  |  |  |  ------ NC - NMI Command
                 |  |  |  |  |  --------- DG - Degate RAM
                 |  |  |  |  ------------ FP - Force Bad Parity
                 |  |  |  --------------- IE - Interrupt Enable
                 |  |  ------------------ IP - Interrupt Pending
                 |  --------------------- RA - RAM Access Error
                 ------------------------ 00 - Reserved
Bit Descriptions:
Bit 7
Reserved (always program to zero)
Bit 6
RAM Access Error (RA)

This bit is valid only after an I/O channel check occurs.

             Bit 6 = 1 indicates a RAM access error
             Bit 6 = 0 indicates a parity error
         
In ether case the address at which the error occurred is latched in the PCPAR0 and PCPAR1 registers. This bit is read-only.
Bit 5
Interrupt Pending (IP)

If an interrupt is pending for the system unit, then IP=1. It is reset to zero when the task register (TREG) is read by the system unit. It is a read-only bit. This bit is also cleared by a channel reset.

Bit 4
Interrupt Enable (IE)

If this bit is set to one, interrupts are enabled. Resetting this bit to zero prevents external interrupts. If an interrupt is pending (IP=1), and this bit is set, an interrupt will occur.

Bit 3
Force Bad Parity (FP)

Setting this bit to one causes all data written from either the system unit or Co-Processor Adapter to have bad parity stored with it. The bit is dual purpose in that it is set to one if the Co-Processor Adapter has its identical `force bad parity' bit (in the NMIMASK) active. This bit only reads zero when both the Co-Processor Adapter and system unit have written zero into their respective bits as indicated in the table below.

System Unit                           System Unit
WR ---------------                    RD ----------------
                 |                                      |     System Unit
System Unit   -------                                -------- Data Bus
Data Bus      |     |      --------                  |      | (FB Bit)
(FP bit) ---->|Latch|----->|      |             ---->|Buffer|----------->
              |     |      |      |             |    |      |
              -------      |      | FP Internal |    --------
                           |  OR  | Control Bit |
                           |      |-------------|             Co-Proc
Co-Proc                    |      |             |             Adapter
Adapter       -------      |      |             |    -------- Data Bus
Data Bus      |     |      |      |             |    |      | (FB Bit)
(FP bit) ---->|Latch|----->|      |             ---->|Buffer|----------->
              |     |      --------                  |      |
              -------                                --------
Co-Proc Adapter  |                    Co-Proc Adapter   |
WR ---------------                    RD ----------------


   IF . . .                          THEN . . .
  -------------------------------   ------------------------------
  | System Unit   AND   Co-Proc |   | System Unit   AND   Co-Proc|
  |   Writes      ---   Writes  |   |    Reads      ---    Reads |
  |-----------------------------|   |----------------------------|
  |     0                 0     |   |     0                  0   |
  |     0                 1     |   |     1                  1   |
  |     1                 0     |   |     1                  1   |
  |     1                 1     |   |     1                  1   |
  -------------------------------   ------------------------------
Bit 2
Degate RAM (DG)

Setting this bit to one deactivates the RAM (prohibits access to the RAM) from the system unit CPU. This bit is dual purpose in that it is set to one if the Co-Processor Adapter has its identical degate RAM bit (in the NMIMASK) active. This bit reads a zero only when both the Co-Processor Adapter and system unit have written zeros into their respective bits, as indicated in the table below. Exercise caution when using this bit. Undetermined behavior of the Shared Storage Interface Chip will occur if this bit is set to one during a system unit memory read or memory write.

System Unit                           System Unit
WR ---------------                    RD ----------------
                 |                                      |     System Unit
System Unit   -------                                -------- Data Bus
Data Bus      |     |      --------                  |      | (DG Bit)
(DG bit) ---->|Latch|----->|      |             ---->|Buffer|----------->
              |     |      |      |             |    |      |
              -------      |      | DG Internal |    --------
                           |  OR  | Control Bit |
                           |      |-------------|             Co-Proc
Co-Proc                    |      |             |             Adapter
Adapter       -------      |      |             |    -------- Data Bus
Data Bus      |     |      |      |             |    |      | (DG Bit)
(DG bit) ---->|Latch|----->|      |             ---->|Buffer|----------->
              |     |      --------                  |      |
              -------                                --------
Co-Proc Adapter  |                    Co-Proc Adapter   |
WR ---------------                    RD ----------------


   IF . . .                          THEN . . .
  -------------------------------   ------------------------------
  | System Unit   AND   Co-Proc |   | System Unit   AND   Co-Proc|
  |   Writes      ---   Writes  |   |    Reads      ---    Reads |
  |-----------------------------|   |----------------------------|
  |     0                 0     |   |     0                  0   |
  |     0                 1     |   |     1                  1   |
  |     1                 0     |   |     1                  1   |
  |     1                 1     |   |     1                  1   |
  -------------------------------   ------------------------------
Bit 1
NMI Command (NC)

Setting this bit to one can cause a NMI to the Co-Processor Adapter. Resetting this bit to zero does not remove the NMI. Resetting this bit to zero is automatically done when the Co-Processor Adapter reads the NMISTAT. Because this bit is affected by the reset command, do not set this bit to one with the same write that clears the reset command (bit 0) to zero.

Example: COMREG data = 0000 0001 and it is desired to clear the reset command (bit 0) to zero and set the NMI (bit 1) to one:

Incorrect:
  System Unit write COMREG data = 0000 0010

Correct:
  System Unit write COMREG data = 0000 0000 (first)
  System Unit write COMREG data = 0000 0010 (second)

Bit 0
Reset Command (RC)

Setting this bit to one causes a partial Shared Storage Interface Chip reset and a hardware reset of the Co-Processor Adapter. The Co-Processor Adapter remains in reset until this bit is reset to zero. This command should be issued for at least one microsecond. The following registers are affected:

            Register After Reset Command

              COMREG   0000 0SS0
              NMIMASK  0011 1111
              NMISTAT  0000 0000
              TREG     1111 1111
          
The following are also reset to zero:
Reset Conditions:
    Power-Up:       0000 0000
    Reset Command:  0000 0SS0

Control Alternate Delete Registers (CAD0, CAD1, CAD2)

Description:

The CAD registers are system unit read/write registers. The feature is activated by writing to CAD2.

The CAD registers are used to detect a system restart. This is done by comparing the values of the CAD registers to the system unit address bus on every valid memory read or write cycle. This value should be an address accessed only when the system unit is restarted using "CTRL-ALT-DEL". When a valid match is found, the system unit side of memory is deactivated. The channel reset is OR'ed with the CAD match signal and therefore will deactivate the Co-Processor Adapter side of memory. Note that the "lower 16 MB indicator" will be gated into the CAD match circuitry. In Co-Processor Adapters with address space greater than 16 MB, the CAD match may be of no use.

I/O Addresses:

 System Unit
         CAD0 = Use DREG with PTRREG preset to 0Ch
         CAD1 = Use DREG with PTRREG preset to 0Dh
         CAD2 = Use DREG with PTRREG preset to 0Eh
 Co-Processor Adapter - None
Register Format:
   -------------------------
   |D7|D6|D5|D4|D3|D2|D1|D0|
   -------------------------
    |  |  |  |  |  |  |  |   CAD0    CAD1    CAD2
    |  |  |  |  |  |  |  --- A0      A8      A16
    |  |  |  |  |  |  ------ A1      A9      A17
    |  |  |  |  |  --------- A2      A10     A18
    |  |  |  |  ------------ A3      A11     A19
    |  |  |  --------------- A4      A12     A20
    |  |  ------------------ A5      A13     A21
    |  --------------------- A6      A14     A22
    ------------------------ A7      A15     A23
Bit Descriptions:
Bits 7-0
System Unit Address Bits

These bits are programmed for the system unit address value that occurs only during a keyboard system restart. Always program CAD2 last, since this activates this feature of the Shared Storage Interface Chip. Once the feature is enabled, it cannot be disabled except by a hardware reset of the system unit. These registers are accessible through the pointer (PTRREG) and data (DREG) registers.

Reset Conditions:
  Power-Up:       0000 0000
  Reset Command:  SSSS SSSS

CPU Page Register (CPUPG)

Description:

The CPUPG register is a read/write register accessible by the system unit or Co-Processor Adapter CPUs. It determines which 8K page of RAM is viewed by the system unit. It is automatically activated on any valid system unit CPU access to the Co-Processor Adapter RAM. It is not accessible from the system unit until the Co-Processor Adapter initializes the INITREG0 register.

I/O Addresses:

 System Unit - CPUPG = Base Address +0005h
 Co-Processor Adapter - CPUPG = 0014h
Register Format:
   -------------------------
   |D7|D6|D5|D4|D3|D2|D1|D0|
   -------------------------
    |  |  |  |  |  |  |  |         Window Size
    |  |  |  |  |  |  |  |   8KB   16KB   32KB   64KB
    |  |  |  |  |  |  |  --- A13   A14    A15    A16
    |  |  |  |  |  |  ------ A14   A15    A16    A17
    |  |  |  |  |  --------- A15   A16    A17    A18
    |  |  |  |  ------------ A16   A17    A18    A19
    |  |  |  --------------- A17   A18    A19    00
    |  |  ------------------ A18   A19    00     00
    |  --------------------- A19   00     00     00
    ------------------------ 00    00     00     00
Bit Descriptions:
Bit 7
Reserved (always program to zero)
Bits 6-0
Page Values

A page value (0-7fh) determines where in the Co-Processor Adapter memory that the system unit may view. To calculate the absolute RAM location addressed within the Co-Processor Adapter memory map (not the absolute RAM location within the system unit memory), the page value may be thought of as providing address lines to the RAM. The number of address lines provided is dependent on the window size. Be aware that if a simultaneous write by the system unit and Co-Processor Adapter occurs, the value of the register is uncertain. The first write to this register by either the system unit or Co-Processor Adapter will activate the RAM on the system unit side if previously deactivated by either a CAD match, power-up, or channel reset. RAM will never be activated before system unit refresh activity is detected or if the sleep bit is active.

Note: It should be noted that dynamically changing the window size will make a corresponding change to the CPU page value. For example, if the window size is set at 8K and CPU page value is 08H, dynamically changing the window to 16K will result in a CPU page value of 04H.

Reset Conditions:
  Power-Up:       UUUU UUUU
  Reset Command:  SSSS SSSS

Adapter ID Register Lower and Upper (CRDIDL, CRDIDU)

Description:

This allows the system unit set-up program to identify the Co-Processor Adapter.

I/O Addresses:

 System Unit -
         POS I/O address OFFSET(CRDIDL)=0000h
         POS I/O address OFFSET(CRDIDU)=0001h
 Co-Processor Adapter -  None
Register Format:
   -------------------------
   |D7|D6|D5|D4|D3|D2|D1|D0|
   -------------------------
    |  |  |  |  |  |  |  |   POS0    POS1
    |  |  |  |  |  |  |  ---   0       1
    |  |  |  |  |  |  ------   0       1
    |  |  |  |  |  ---------   0       1
    |  |  |  |  ------------   0       1
    |  |  |  ---------------   1       0
    |  |  ------------------   1       1
    |  ---------------------   1       1
    ------------------------   1       1
Reset Conditions:
                  POS0             POS1
  Power-Up:       1111 0000        1110 1111
  Reset Command:  SSSS SSSS        SSSS SSSS

Data Register (DREG)

Description:

The system unit DREG is a pseudo register. It is a window to a variety of registers, only one of which is enabled at a time by the PTRREG. Read and write characteristics are determined by the characteristics of the register enabled by the PTRREG.

I/O Addresses:

 System Unit - DREG = Base Address +0003h
 Co-Processor Adapter -  None
Register Format:
   -------------------------
   |D7|D6|D5|D4|D3|D2|D1|D0|
   -------------------------
    |  |  |  |  |  |  |  |
    |  |  |  |  |  |  |  --- D0
    |  |  |  |  |  |  ------ D1
    |  |  |  |  |  --------- D2
    |  |  |  |  ------------ D3
    |  |  |  --------------- D4
    |  |  ------------------ D5
    |  --------------------- D6
    ------------------------ D7
Bit Descriptions:
Bits 7-0
Data Bits

Data is variable depending upon the register enabled by PTRREG.

Reset Conditions:
    Power-Up:       UUUU UUUU
    Reset Command:  UUUU UUUU

Gate Array Identification Register (GAID)

Description:

This register allows either the system unit or the Co-Processor Adapter to determine which Shared Storage Interface Chip (1, 2, or 3) is being used on the adapter. It is a read-only register. It is not accessible until the Co-Processor Adapter initializes the INITREG0 register.

I/O Addresses:

 System Unit
         GAID =  Use DREG with PTRREG preset to 0Fh
 Co-Processor Adapter
         GAID = 0018h
Register Format:
   -------------------------
   |D7|D6|D5|D4|D3|D2|D1|D0|
   -------------------------
    |  |  |  |  |  |  |  |   SSTIC1   SSTIC2   SSTIC3
    |  |  |  |  |  |  |  ---   0        0        0
    |  |  |  |  |  |  ------   0        0        0
    |  |  |  |  |  ---------   0        0        0
    |  |  |  |  ------------   0        0        0
    |  |  |  ---------------   0        1        0
    |  |  ------------------   0        1        0
    |  ---------------------   0        0        1
    ------------------------   0        0        1
Bit Descriptions:
Bits 7-0
Gate Array Identification

If the gate array is the SSTIC1, the value read will be a 00h. If the gate array is the SSTIC2, the value read will be a 30h. SSTIC3 has a value of C0h. Realtime Interface Co-Processor Multiport/2 uses SSTIC3.

Reset Conditions:
                   SSTIC1        SSTIC2        SSTIC3

  Power-Up:       0000 0000     0011 0000     1100 0000
  Reset Command:  SSSS SSSS     SSSS SSSS     SSSS SSSS

Internal DAL Register (IDAL)

Description:

The IDAL is a copy of the external DAL register used on the Realtime Interface Co-Processor.

I/O Addresses:

 System Unit - None
 Co-Processor Adapter
         IDAL = 0084h
Register Format:
   -------------------------
   |D7|D6|D5|D4|D3|D2|D1|D0|
   -------------------------
    |  |  |  |  |  |  |  |
    |  |  |  |  |  |  |  --- 00
    |  |  |  |  |  |  ------ 00
    |  |  |  |  |  --------- 00
    |  |  |  |  ------------ ND
    |  |  |  --------------- R0
    |  |  ------------------ R1
    |  --------------------- R2
    ------------------------ R3
Bit Descriptions:
Bits 7-4
DAL control

See the DAL section for explanation.

Bit 3
Reserved. Any value may be programmed, but it will not be retained.
Bits 2-0
Reserved. Always program to a zero.
Reset Conditions:
    Power-Up:       0000 0000
    Reset Command:  0000 0000

Co-Processor Adapter Parity Registers (ICAPAR0, 1, 2)

Description:

The ICAPAR registers are used to capture the Co-Processor Adapter status and address at which a parity error or RAM access error occurs. They are read-only registers. The data in these registers is valid only if the PE bit is set in the NMISTAT register. In order for internal circuitry to be cleared and for further parity checking to be allowed, ICAPAR2 must be read. It is suggested that ICAPAR0 and ICAPAR1 be read before ICAPAR2 since the ICAPAR2 read releases all three registers to capture an address if another error should occur.

I/O Addresses:

 System Unit - None

 Co-Processor Adapter
          ICAPAR0 = 000Ch
          ICAPAR1 = 000Eh
          ICAPAR2 = 0010h
Register Format:
   -------------------------
   |D7|D6|D5|D4|D3|D2|D1|D0|
   -------------------------
    |  |  |  |  |  |  |  |   ICAPAR0  ICAPAR1  ICAPAR2
    |  |  |  |  |  |  |  ---   A0       A8       A16
    |  |  |  |  |  |  ------   A1       A9       A17
    |  |  |  |  |  ---------   A2       A10      A18
    |  |  |  |  ------------   A3       A11      A19
    |  |  |  ---------------   A4       A12      DMA
    |  |  ------------------   A5       A13      RA
    |  ---------------------   A6       A14      00
    ------------------------   A7       A15      00
Bit Descriptions - ICAPAR0 and ICAPAR1:
Bits 7-0
Co-Processor Adapter Address Bits

These bits represent the address at which a parity error occurred.

Bit Descriptions - ICAPAR2:
Bits 7-6
Reserved (always zero)
Bit 5
RAM Access Error (RA)

If a RAM Access Error occurred, RA=1; otherwise, RA=0 to indicate a parity error. A RAM Access Error is detected when the Shared Storage Interface Chip Co-Processor Adapter SRDY signal is inactive for more than 15 Co-Processor Adapter clock cycles. If this occurs, RA is set to one, the Co-Processor Adapter SRDY signal is released, a Co-Processor Adapter parity error is generated, and the present Co-Processor Adapter address and status are latched, including this bit.

Bit 4
DMA/CPU Status (DMA)

If this bit is set to one, then a DMA cycle created the parity error. If this bit is reset to zero, then a CPU cycle created the error.

Bits 3-0
Co-Processor Adapter Address Bits

The four most significant bits of the address at which the parity error occurred.

Reset Conditions:
  Power-Up:       0000 0000
  Reset Command:  SSSS SSSS

Initialization Registers (INITREG0, 1, 2, 3)

Description:

The INITREG0, 1, and 3 are Co-Processor Adapter and system unit read/write registers. INITREG2 is a system unit read-only register. Their purpose is to initialize the Shared Storage Interface Chip for proper operation. INITREG0 and 3 should be programmed by POS. (offset 2 and 5). POS address offsets are further qualified by a valid CARDEN.) INITREG1 should be programmed by the co-processor adapter.

I/O Addresses:

 System Unit
    INITREG0    PTRREG = Use DREG with PTRREG preset to 12h
    INITREG1    PTRREG = Use DREG with PTRREG preset to 10h
    INITREG2    PTRREG = Use DREG with PTRREG preset to 08h
    INITREG3    PTRREG = Use DREG with PTRREG preset to 13h

 Co-Processor Adapter
    INITREG0 = 0004h
    INITREG1 = 0006h
    INITREG3 = 001Ah
Register Format:
   -------------------------
   |D7|D6|D5|D4|D3|D2|D1|D0|
   -------------------------
    |  |  |  |  |  |  |  |
    |  |  |  |  |  |  |  |  INITREG0 INITREG1 INITREG2 INITREG3
    |  |  |  |  |  |  |  ---   L1       XX       L1       W1
    |  |  |  |  |  |  ------   L2       XX       L2       W2
    |  |  |  |  |  ---------   L4       XX       L4       W4
    |  |  |  |  ------------   SE       M1       00       00
    |  |  |  ---------------   C1       LN       00       00
    |  |  ------------------   C2       M2       00       00
    |  ---------------------   C4       RR       00       00
    ------------------------   C8       DR       00       00
POS2 is mapped into INITREG0. Thus, when INITREG0 address or POS address is used, the same register is accessed. POS5 is mapped into INITREG3 and PCPAR2. The arrangement is shown in the following tables. CKS has no need to be in INITREG3 or PCPAR2.
    --------------------  ------------------------------
    | POS2 -> INITREG0 |  | POS5 -> INITREG3 -> PCPAR2 |
    |                  |  |                            |
    |  SE        L1    |  |  W1        W1         IEN  |
    |  L1        L2    |  |  W2        W2         IPS  |
    |  L2        L4    |  |  W4        W4         CKI  |
    |  L4        SE    |  |  00        00         00   |
    |  C1        C1    |  |  00        00         00   |
    |  C2        C2    |  |  00        00         00   |
    |  C4        C4    |  |  CKS       00         00   |
    |  C8        C8    |  |  NCKI      00         00   |
    --------------------  ------------------------------
Bit Descriptions - INITREG0 and INITREG2:
Bits 7-4
Adapter number Settings (C1-C8)

These bits specify the system unit base I/O address for all system unit Shared Storage Interface Chip I/O registers. Each adapter should have a unique address, with respect to other adapters and any other attachment in the system unit. These bits read zero from the system unit side.

                -------------
                |C8|C4|C2|C1|  Co-Processor
                -------------    Address
                 |  |  |  |

                 0  0  0  0       02A0H
                 0  0  0  1       06A0H
                 0  0  1  0       0AA0H
                 0  0  1  1       0EA0H
                 0  1  0  0       12A0H
                 0  1  0  1       16A0H
                 0  1  1  0       1AA0H
                 0  1  1  1       1EA0H
                 1  0  0  0       22A0H
                 1  0  0  1       26A0H
                 1  0  1  0       2AA0H
                 1  0  1  1       2EA0H
                 1  1  0  0       32A0H
                 1  1  0  1       36A0H
                 1  1  1  0       3AA0H
                 1  1  1  1       3EA0H
         
Bit 3
Sleep Enable (SE)

This bit is defined in the micro-channel to disable the attachment adapter from the system unit bus when cleared. It is cleared on a channel reset.

Bits 2-0
Interrupt Level (L1, L2, L4)

These determine the interrupt level at which the Co-Processor Adapter operates within the system unit environment.

                ----------
                |L4|L2|L1|  Interrupt Level
                ----------     (Decimal)
                 |  |  |

                 0  0  0         3
                 0  0  1         4
                 0  1  0         7
                 0  1  1         2 or 9
                 1  0  0         10
                 1  0  1         11
                 1  1  0         12
                 1  1  1         15
         
Bit Descriptions - INITREG 1:
Bit 7
Double Refresh Time

When cleared, the refresh rate will be 7.8 microseconds. When set, the refresh rate will be 15.6 microseconds. The RAM bandwidth gain is only 2% at the 15.6 rate.

Bit 6
ROS Ready

Reset by power-up. Responsibility of PROM to set after it is ready. May be cleared by PROM if desired.

Bit 5
Memory Size

( 0 = 960KB; 1 = 512KB ) Note: If Bit 3=1, this bit is a don't care.

Bit 4
Lost Refresh Disable

This bit is set to one to disable the lost refresh feature. Resetting this bit to zero enables lost refresh.

Bit 3
Memory Size

( 0 = 512KB; 1 = 128KB or 960KB dependent on Bit 5 )

Bits 2-0
Reserved

May be programmed to any value. This is to help the PROM microcode program both SSTIC2 and SSTIC3. Will not retain the value.

Bit Descriptions - INITREG 3:
Bits 7-3
Reserved

Always program to zero.

Bits 2-0
Window Size

This value selects the window size that the system unit views at any one time. 8KB is the default for compatibility. All other values are reserved.

                   -------------------
                   | W4 W2 W1 | Size |
                   |----------+------|
                   | 0  0  0  |  8KB |
                   | 0  0  1  | 16KB |
                   | 0  1  0  | 32KB |
                   | 0  1  1  | 64KB |
                   -------------------
        
Reset Conditions:

                  INITREG0    INITREG1    INITREG2    INITREG3
  Power-Up:       0000 0000   0000 0000   0000 0000   0000 0000
  Reset Command:  SSSS SSSS   SSSS SSSS   SSSS SSSS   SSSS SSSS

Location Registers (LOCREG0, LOCREG1)

Description:

The location registers are system unit and Co-Processor Adapter read/write registers. They provide the option to place the Co-Processor Adapter memory anywhere in the system unit 16MB memory map on a boundary defined by W4,W2, and W1 in INITREG3. Never change the location registers without deactivating the system unit side of RAM. If a simultaneous write by the system unit and Co-Processor Adapter occurs, the value of the register is uncertain. Normal operation is for POS to initialize LOCREG0 and 1 at address offsets 3 and 4. POS address offsets are further qualified by CARDEN.

I/O Addresses:

 System Unit - LOCREG0 = Base Address +0000h
          LOCREG1 = Base Address +0001h
 Co-Processor Adapter - LOCREG0 = 0000h
        LOCREG1 = 0002h
Register Format:
   -------------------------
   |D7|D6|D5|D4|D3|D2|D1|D0|
   -------------------------
    |  |  |  |  |  |  |  |    POS3       POS4
    |  |  |  |  |  |  |  |   LOCREG0    LOCREG1
    |  |  |  |  |  |  |  ---   A13        A20
    |  |  |  |  |  |  ------   A14        A21
    |  |  |  |  |  ---------   A15        A22
    |  |  |  |  ------------   A16        A23
    |  |  |  ---------------   A17        00
    |  |  ------------------   A18        00
    |  ---------------------   A19        00
    ------------------------   00         00
Bit Descriptions - LOCREG0:
Bit 7
Reserved (always program to zero)
Bits 6-0
Address Bits

LOCREG0 must match system unit address bits A19 to A13 to access the Co-Processor Adapter RAM. This value is where the user desires the Co-Processor Adapter to be located within the system unit memory map. 16KB boundaries do not use A13. 32KB boundaries do not use A13 and A14. 64KB boundaries do not use A13, A14, and A15.

Note: If the window size is changed dynamically, the user must keep track of where the boundary of the window has been changed to. For example, if there is an 8K window initially at C200H segment (61H) and the size is changed to a 16K window, the new segment would be at C000H (60H).

Bit Descriptions - LOCREG1:
Bits 7-4
Reserved (always zero)
Bits 3-0
Address Bits

LOCREG1 is a continuation of LOCREG0. Program the value that corresponds to the desired location for the Co-Processor Adapter within the system unit memory map.

Reset Conditions:
    Power-Up:       UUUU UUUU
    Reset Command:  UUUU UUUU

NMI Mask Register (NMIMASK)

Description:

The NMIMASK is a Co-Processor Adapter read/write register. Its purpose is to allow masking of the various sources of interrupts from causing an NMI to the Co-Processor Adapter CPU.

I/O Addresses:

 System Unit - None (see COMREG)
 Co-Processor Adapter - NMIMASK = 0008h
Register Format:
   -------------------------
   |D7|D6|D5|D4|D3|D2|D1|D0|
   -------------------------
    |  |  |  |  |  |  |  |
    |  |  |  |  |  |  |  --- CAD/CRST
    |  |  |  |  |  |  ------ WD  - Watchdog Timer
    |  |  |  |  |  --------- PE  - Parity Error
    |  |  |  |  ------------ PS/2- I/O Channel Check
    |  |  |  --------------- NC  - NMI Command
    |  |  ------------------ LR  - Lost Refresh
    |  --------------------- DG  - Degate RAM
    ------------------------ FP  - Force Bad Parity
Bit Descriptions:
Bit 7
Force Bad Parity (FP)

Setting this bit to one causes all data written from either the system unit or Co-Processor Adapter to have bad parity stored. This bit is dual purpose in that it is set to one if the system unit has its identical "force bad parity" bit active in the COMREG register. This bit only reads a zero when both the Co-Processor Adapter and system unit have written zero into their respective bits as indicated in the table below.

System Unit                        System Unit
WR --------------                 RD ----------------
                |                                   |   System Unit
System Unit  -------                             -------- Data Bus
Data Bus     |     |    -------                  |      | (FB Bit)
(FP bit) --->|Latch|--->|     |             ---->|Buffer|--------->
             |     |    |     |             |    |      |
             -------    |     | FP Internal |    --------
                        | OR  | Control Bit |
                        |     |-------------|             Co-Proc
Co-Proc                 |     |             |             Adapter
Adapter      -------    |     |             |    -------- Data Bus
Data Bus     |     |    |     |             |    |      | (FB Bit)
(FP bit) --->|Latch|--->|     |             ---->|Buffer|--------->
             |     |    -------                  |      |
             -------                             --------
Co-Proc Adapter |                 Co-Proc Adapter   |
WR --------------                 RD ----------------



   IF . . .                         THEN . . .
  -------------------------------  ------------------------------
  | System Unit   AND   Co-Proc |  | System Unit   AND   Co-Proc|
  |   Writes      ---   Writes  |  |    Reads      ---    Reads |
  |-----------------------------|  |----------------------------|
  |     0                 0     |  |     0                  0   |
  |     0                 1     |  |     1                  1   |
  |     1                 0     |  |     1                  1   |
  |     1                 1     |  |     1                  1   |
  -------------------------------  ------------------------------
Bit 6
Degate RAM (DG)

Setting this bit deactivates the RAM (prohibits access to the RAM from the system unit CPU). This bit is dual purpose in that it is set to one if the system unit has its identical degate RAM bit (in the COMREG) active. This bit reads only a zero when both the Co-Processor Adapter and system unit have written zeros into their respective bits, as indicated in the table below. Caution should be exercised when using this bit. Undetermined behavior of the Shared Storage Interface Chip occurs if this bit is set to one during a system unit memory read or memory write.

System Unit                        System Unit
WR --------------                 RD ----------------
                |                                   |   System Unit
System Unit  -------                             -------- Data Bus
Data Bus     |     |    -------                  |      | (DG Bit)
(DG bit) --->|Latch|--->|     |             ---->|Buffer|--------->
             |     |    |     |             |    |      |
             -------    |     | DG Internal |    --------
                        | OR  | Control Bit |
                        |     |-------------|             Co-Proc
Co-Proc                 |     |             |             Adapter
Adapter      -------    |     |             |    -------- Data Bus
Data Bus     |     |    |     |             |    |      | (DG Bit)
(DG bit) --->|Latch|--->|     |             ---->|Buffer|--------->
             |     |    -------                  |      |
             -------                             --------
Co-Proc Adapter |                 Co-Proc Adapter   |
WR --------------                 RD ----------------



   IF . . .                         THEN . . .
  -------------------------------  ------------------------------
  | System Unit   AND   Co-Proc |  | System Unit   AND   Co-Proc|
  |   Writes      ---   Writes  |  |    Reads      ---    Reads |
  |-----------------------------|  |----------------------------|
  |     0                 0     |  |     0                  0   |
  |     0                 1     |  |     1                  1   |
  |     1                 0     |  |     1                  1   |
  |     1                 1     |  |     1                  1   |
  -------------------------------  ------------------------------
Bit 5
Lost Refresh Mask Bit (LR)

This condition occurs if the system unit stops refreshing RAM. If this bit is set to one, the lost refresh indicator is masked from creating a NMI. If this bit is a zero, the lost refresh indicator is allowed to create a NMI to the Co-Processor Adapter CPU. In either case, the lost refresh is posted in the NMISTAT register.

Bit 4
NMI Command Mask Bit (NC)

An NMI command may be given by the system unit through its COMREG register. The Co-Processor Adapter has the option of masking this command from creating a NMI by setting this bit to one. If this bit is a zero, a NMI is created when the system unit issues this command. In either case, a parity error is posted in the NMISTAT register.

Bit 3
System Unit I/O Channel Check Mask Bit (ICC)

The Shared Storage Interface Chip monitors the system unit I/O channel check line. The Co-Processor Adapter has the option of masking this status from creating a NMI by setting this bit. If this bit is a zero, a NMI is created when this line is active. In either case, the ICC is posted in the NMISTAT register.

Bit 2
Co-Processor Adapter Parity Error Mask Bit (PE)

When the Co-Processor Adapter CPU or DMA cycle has a parity error or RAM access error, the Co-Processor Adapter has the option of masking this status from creating a NMI by setting this bit to one. If this bit is a zero, a NMI is created when a parity error or RAM access error occurs. In either case, a PE is posted in the NMISTAT registers.

Bit 1
Watchdog Timer Error Mask Bit (WD)

The Shared Storage Interface Chip monitors the watchdog timer on the Co-Processor Adapter.

When the watchdog timer has an error, the Co-Processor Adapter has the option of masking this status from creating a NMI by setting this bit to one. If this bit is a zero and a watchdog error occurs, a NMI is created, the task register is loaded with a FE hex value, and a system unit interrupt is generated.

If the watchdog timer error mask bit is set, the NMI is blocked, the task register is not loaded, and a system unit interrupt is not generated. See the task register (TREG).

In either case, a WD is posted in the NMISTAT registers.

Bit 0
CTRL-ALT-DEL Match/Channel Reset Mask Bit (CAD)

When a CTRL-ALT-DEL match occurs on the system unit side, or when a system unit channel reset occurs during a warm start, the Co-Processor Adapter has the option of masking this status from creating a NMI by setting this bit to one. If this bit is a zero, an NMI is created when a CAD match occurs. In either case, a CAD is posted in the NMISTAT register.

Reset Conditions:
    Power-Up:       0011 1111
    Reset Command:  0011 1111

NMI Status Register (NMISTAT)

Description:

The NMISTAT is a Co-Processor Adapter read-only register. Its purpose is to provide status of the various NMI interrupts that can occur. The internal status latches are edge sensitive, not level sensitive. Once a bit is active, the Co-Processor Adapter must read the NMISTAT, the status bit must go inactive, and then go active to be detected once again. Two bits are not NMI status bits, but system unit interrupt status bits.

I/O Addresses:

 System Unit - None
 Co-Processor Adapter - NMISTAT = 000Ah
Register Format:
   -------------------------
   |D7|D6|D5|D4|D3|D2|D1|D0|
   -------------------------
    |  |  |  |  |  |  |  |
    |  |  |  |  |  |  |  --- CAD/CRST
    |  |  |  |  |  |  ------ WD  - Watchdog Timer
    |  |  |  |  |  --------- PE  - Parity Error
    |  |  |  |  ------------ PS/2 - I/O Channel Check
    |  |  |  --------------- NC  - NMI Command
    |  |  ------------------ LR  - Lost Refresh
    |  --------------------- IE  - Interrupt Enable
    ------------------------ IP  - Interrupt Pending
Bit Descriptions:
Bit 7
Interrupt Pending (IP)

If an interrupt is pending for the system unit, then IP=1. It is reset to zero by reading the task register.

Bit 6
Interrupt Enable (IE)

If this bit is set to one, system unit interrupts are enabled.

Bit 5
Lost Refresh Status (LR)

If this bit is set to one, the system unit has lost refresh. This bit is reset to zero by reading this register, which also terminates the NMI.

Bit 4
NMI Command Status (NC)

If this bit is set to one, the system unit has issued a NMI command. This bit is reset to zero by reading this register, which also terminates the NMI.

Bit 3
System Unit I/O Channel Check Status (ICC)

If this bit is set to one, the system unit has an I/O channel check. This bit is reset to zero by reading this register, which also terminates the NMI.

Bit 2
Co-Processor Adapter Parity Error Status (PE)

If this bit is set to one, the Co-Processor Adapter has a parity error or RAM access error (see ICAPAR). This bit is reset to zero by reading this register, which also terminates the NMI.

Bit 1
Watchdog Timer Error Status (WD)

If this bit is set to one, the Co-Processor Adapter has a watchdog time error. This bit is reset to zero by reading this register, which also terminates the NMI.

Bit 0
CTRL-ALT-DEL Match Status (CAD)

If this bit is set to one, the system unit has a CAD match or a system unit channel reset from a warm start. This bit is reset to zero by reading this register, which also terminates the NMI.

Reset Conditions:
    Power-Up:       0000 0000
    Reset Command:  0000 0000

System Unit Parity Registers (PCPAR0, PCPAR1)

Description:

The PCPAR registers are used to capture the system unit address and status at which a parity error occurs. They are read-only. The data in these registers is only valid after an error. In order for internal circuitry to be cleared and to allow for further parity checking, a system unit memory write to the Co-Processor Adapter must be performed or POS5 Bit 7 must be written with a one. It can be to any location. These two registers should be used in conjunction with the CPUPG register to determine where the error occurred.

I/O Addresses:

 System Unit
                 PCPAR0 = Use DREG with PTRREG preset to 0Ah
                 PCPAR1 = Use DREG with PTRREG preset to 0Bh
                 PCPAR2 = Use DREG with PTRREG preset to 11h

 Co-Processor Adapter - None
Register Format:
   -------------------------
   |D7|D6|D5|D4|D3|D2|D1|D0|
   -------------------------
    |  |  |  |  |  |  |  |   PCPAR0  PCPAR1  PCPAR2
    |  |  |  |  |  |  |  ---  A0      A8      IEN
    |  |  |  |  |  |  ------  A1      A9      IPS
    |  |  |  |  |  ---------  A2      A10     CKI
    |  |  |  |  ------------  A3      A11     0
    |  |  |  ---------------  A4      A12     0
    |  |  ------------------  A5      A13     0
    |  ---------------------  A6      A14     0
    ------------------------  A7      A15     0
Bit Descriptions - PCPAR0:
Bits 7-0
System Unit Address Bits (A0-A7)

These bits represent the address at which a parity error occurred.

Bit Descriptions - PCPAR1:
Bits 7-5
System Unit Address Bits

These bits are available only when an expanded window size is being used.

Bits 4-0
System Unit Address Bits (A8-A12)

These bits represent the most significant five bits of the address at which a parity error occurred.

Bit Descriptions - PCPAR2:
Bits 7-3
System Unit Reserved

Always program these bits to zero.

Bit 2
I/O Channel Check Status

This bit is a read-only bit indicating if an I/O channel check condition exists. This bit always indicates status regardless of the state of bits 0 or 1. To clear this bit, write to any memory location in the Co-Processor Adapter memory. Either a channel reset or writing a "1" to POS5 Bit 7 will clear this bit. This bit is the inversion of POS bit NCKI.

Bit 1
I/O Channel Check Pulse Mode

When this bit is set, I/O channel check will be pulsed when a parity error occurs. When this bit is cleared, I/O channel check will stay active low when a parity error occurs. This bit powers up a zero and should never be programmed to a one.

Bit 0
I/O Channel Check Enable

When this bit is set, the I/O channel check line is enabled to report parity errors. When cleared, parity errors will not be reported except by bit 2.

Reset Conditions:
                   PCPAR0       PCPAR1       PCPAR2
  Power-Up:       0000 0000    0000 0000    0000 0001
  Reset Command:  SSSS SSSS    SSSS SSSS    SSSS SSSS

Pointer Register (PTRREG)

Description:

The PTRREG is a system unit read/write register. It enables other system unit registers to be accessed through the data registers (DREG). Only one register is enabled at a time, based on the value in the PTRREG. Once programmed with a value, the enabled register may be accessed multiple times, provided that the PTRREG is not changed during that time. Individual registers accessed are discussed separately.

I/O Addresses:

 System Unit - PTRREG = Base Address +0002h
 Co-Processor Adapter - None
Register Format:
   -------------------------
   |D7|D6|D5|D4|D3|D2|D1|D0|
   -------------------------
    |  |  |  |  |  |  |  |
    |  |  |  |  |  |  |  --- R0
    |  |  |  |  |  |  ------ R1
    |  |  |  |  |  --------- R2
    |  |  |  |  ------------ R3
    |  |  |  --------------- R4
    |  |  ------------------ R5
    |  --------------------- R6
    ------------------------ R7
Bit Descriptions:
Bits 7-0
Register Value

These bits refer to the value needed in the PTRREG to access a particular register through the DREG. Reserved registers should not be used since results are unpredictable.

             ---------------------------------
             |   R7-0  | Register/Function   |
             |---------+---------------------|
             | (00-07) | Reserved            |
             |   (08)  | INITREG2            |
             |   (09)  | Reserved for INTCOM |
             |   (0A)  | PCPAR0              |
             |   (0B)  | PCPAR1              |
             |   (0C)  | CAD0                |
             |   (0D)  | CAD1                |
             |   (0E)  | CAD2                |
             |   (0F)  | GA ID               |
             |   (10)  | INITREG1            |
             |   (11)  | PCPAR2              |
             |   (12)  | INITREG0            |
             |   (13)  | INITREG30           |
             | (14-FF) | Reserved            |
             ---------------------------------
         
Reset Conditions:
    Power-Up:       UUUU UUUU
    Reset Command:  UUUU UUUU

SCC Register (SCCREG)

Description:

Designed to provide various clocking options for Ports 0 and 1. Bits D0-D2 are mapped from POS4. Bits D3-D5 are mapped from POS5. These six bits are writable only from POS. Once written, they may be read via a 16-bit I/O read at 880h from Multiport/2 side. All other bits in this register should be considered to be undefined.

I/O Addresses:

 System Unit - None
 Co-Processor Adapter - SCCREG = 0880h
Register Format:
-------------------------------------------------------
|D15|D14|D13|D12|D11|D10|D9|D8|D7|D6|D5|D4|D3|D2|D1|D0|
-------------------------------------------------------
  |   |   |   |   |   |  |  |  |  |  |  |  |  |  |  |
  |   |   |   |   |   |  |  |  |  |  |  |  |  |  |  --- PLL/32-0
  |   |   |   |   |   |  |  |  |  |  |  |  |  |  ------ LOCAL-0
  |   |   |   |   |   |  |  |  |  |  |  |  |  --------- DCE/DTE-0
  |   |   |   |   |   |  |  |  |  |  |  |  ------------ PLL/32-1
  |   |   |   |   |   |  |  |  |  |  |  --------------- LOCAL-1
  |   |   |   |   |   |  |  |  |  |  ------------------ DCE/DTE-1
  |   |   |   |   |   |  |  |  |  --------------------- Reserved
  |   |   |   |   |   |  |  |  ------------------------ Reserved
  |   |   |   |   |   |  |  --------------------------- 0
  |   |   |   |   |   |  ------------------------------ Reserved
  |   |   |   |   |   --------------------------------- 0
  |   |   |   |   ------------------------------------- Reserved
  |   |   |   ----------------------------------------- 0
  |   |   --------------------------------------------- Reserved
  |   ------------------------------------------------- 0
  ----------------------------------------------------- Reserved
Reset Conditions:
  Power-Up:       X0X0 X0X0 XX00 0000
  Reset Command:  XSXS XSXS XXSS SSSS

Task Register (TREG)

Description:

The TREG is a system unit and Co-Processor Adapter read/write register. It is a mailbox for passing data primarily from the Co-Processor Adapter to the system unit. Writing to this register from either the system unit or Co-Processor Adapter generates an interrupt for the system unit (maskable by the IE bit.) To clear the interrupt, either the Co-Processor Adapter or system unit must read the TREG.

In addition, the act of reading this register will change the value of the register to FFh. A watchdog timer error will also change the value of the register to FEh, but any data written to the Task register, before or after the watchdog timer error occurred, will be saved. After the FEh is read, this data may be read from the TREG. All interrupt functions explained above are true if watchdog timer errors occur. (Interrupts are triggered just as if TREG was written to.) Be aware that if a simultaneous write by the system unit and Co-Processor Adapter occurs, the value of the TREG is uncertain. The TREG is available on the Co-Processor Adapter side at 0016h (read-only) for manufacturing tests only. This is a direct tap of the register and reading it will not change the value of TREG, as does the real TREG address. A channel reset will change the value back to FFh.

I/O Addresses:

 System Unit - TREG = Base address +0004h
 Co-Processor Adapter - TREG = 0012h
Register Format:
   -------------------------
   |D7|D6|D5|D4|D3|D2|D1|D0|
   -------------------------
    |  |  |  |  |  |  |  |
    |  |  |  |  |  |  |  --- T0
    |  |  |  |  |  |  ------ T1
    |  |  |  |  |  --------- T2
    |  |  |  |  ------------ T3
    |  |  |  --------------- T4
    |  |  ------------------ T5
    |  --------------------- T6
    ------------------------ T7
Bit Descriptions:
Bits 7-0
Task Register Data

Any task ID value except:

           FFh - used as the default value
           FEh - used for the watchdog timer error
         
                    ----------        ----------- To Co-Proc
                    |        |        |         | Adapter
          FE hex -->|        | TREG   | Content |--------------->
                    | Multi- | Value  | of TREG |
 (Latched   T0-7 -->| plexer |------->| at time | To System Unit
  Data)             |        |        | of Read |--------------->
          FE hex -->|        |        |         |
                    ----------        -----------
                      |    |
                      |    |
  WDOG Error ----------    |
                           |
  Data Present -------------


    WDOG         Data           TREG Value
    Error        Present        At Time of Read
    -------------------------------------------
    No           No     ---->       FF hex
    No           Yes    ---->       T0 - 7
    Yes          No     ---->       FE hex
    Yes          Yes    ---->       FE hex
Reset Conditions:
  Power-Up:       1111 1111
  Reset Command:  1111 1111

SHARED STORAGE INTERFACE CHIP COMMANDS

This section describes the commands associated with the Shared Storage Interface Chip.

Shared Storage Interface Chip End of Interrupt Command (GEOI)

Description:

The GEOI is a Co-Processor Adapter command used to clear internal interrupt circuitry. It is used after a standard interrupt to the 80186 of the Co-Processor Adapter. No further standard interrupts can occur until this command is given. It is a write-only command. (Reads are reserved and should not be performed.)

I/O Addresses:

 System Unit - None
 Co-Processor Adapter - GEOI = 0016h
Register Format:
   -------------------------
   |D7|D6|D5|D4|D3|D2|D1|D0|
   -------------------------
    |  |  |  |  |  |  |  |

     No data is involved
Reset Conditions: Not applicable

Interrupt Command (INTCOM)

Description:

The interrupt command is a system unit write-only command. It is used to cause a standard interrupt to the 80186 of the Co-Processor Adapter. Multiple interrupt commands cause multiple standard interrupts if the Co-Processor Adapter issues the GEOI command each time.

I/O Addresses:

 System Unit - INTCOM = Base Address +0002h
 Co-Processor Adapter - None
Register Format:
   -------------------------
   |D7|D6|D5|D4|D3|D2|D1|D0|
   -------------------------
    |  |  |  |  |  |  |  |
    |  |  |  |  |  |  |  --- 1
    |  |  |  |  |  |  ------ 0
    |  |  |  |  |  --------- 0
    |  |  |  |  ------------ 1
    |  |  |  --------------- 0
    |  |  ------------------ 0
    |  --------------------- 0
    ------------------------ 0
Bit Descriptions:
Bits 7-0
Data Value = 09h
Reset Conditions: Not Applicable

Last modified: March 25, 1999