WD9500 (PWGA) Enhanced 8514/A Compatible Chip Set Datasheet
WD9500 Architecture
PAM Functional Organization
WD95C00 Pixel Address Manager (PAM)
WD95C01 Pixel Data Manager (PDM)
WD9500 MCA Adapters
WD9500 Architecture

PAM - Pixel Address Manager
PDM - Pixel Data Manager
PAM Functional Organization

WD95C00 Pixel Address Manager (PAM)
The Pixel Address Manager (PAM) of the WD9500 chip set contains:
CPU Interface Unit (CIU), which controls communication with the
system bus (via the CPU interface logic block external to the chip set), and
passes data to and from all the other units on the chip set. It also performs
certain miscellaneous functions, such as forwarding addresses from the system
bus to the EPROM.
Graphics Processor (GP), which performs the actual drawing
computations. It supports all 8514/A graphics modes plus Western Digital
extensions. The modes include line drawing, area fill, area outline drawing
(arbitrary polygons), rectangle drawing, image transfer from the CPU, BITBLT
copying (Bit Block Transfer within VRAM), and scissoring. The GP receives its
drawing instructions from the CIU and sends the resulting pixels coordinates to
the MIC.
Memory Interface Controller (MIC), which controls VRAM addressing and
access. In a typical drawing operation, it converts the DP supplied pixel
coordinates into VRAM addresses, causes the VRAM to send the addressed data
(pixel color values) to the DP for modification, and then rewrites them back
into VRAM. When not involved in a drawing or special-purpose access, the MIC
manages the VRAM addressing portion of the constantly on-going screen refresh
process. The MIC gives screen refresh the highest priority for VRAM access;
next is timer-based VRAM chip refresh. DP-requested drawing access has the
lowest priority.
WD95C01 Pixel Data Manager (PDM)
The Pixel Data Manager (PDM) of the WD9500 chip set contains:
Data Processor (DP), which is responsible for updating VRAM in
support of drawing and data transfer operations and altering pixel data (color
values) according to masks and parameters, including "mix" specifications
supplied in shared internal registers by the DP and GP. The DP receives pixel
data on a bidirectional bus from the VRAM, modifies it, and then writes it back
to the VRAM on the same bus.
Display Processor (DSP), which manages the DAC and monitor,
coordinating its role in the screen refresh process with the MIC. With an
integrated back-end VRAM design, the DSP serializes and multiplexes pixel data
("pumped" out of VRAM by the MIC) to the DAC in synchronization with the timing
of the monitor's sweep across the display screen. (With external back-end
support, this DSP function is assumed by external logic within the VRAM block
and the DAC).
WD9500 MCA Adapters
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