IrisVision Spotting Guide

This page will help you identify and understand the operation of the IRISVISION graphics adapter system. In the block diagram below, you can click on each of the subsystem blocks to find out about its function and see a picture of the card itself. Each image thumbnail can be selected to view a full size image of the card.

MGE:MGE image

This is the MicroChannel Geometry Engine. It is based upon the HQ integer processor from SGI (rated at 10 MIPS) and the Weitek XL-3132 floating point processor (rated at 20 MFLOPS). The geometry engine provides the host interface, handles DMA operations, and handles all the matrix operations, lighting and coordinate transformations.

IBM FRU: 42F6842
ADF:     8EE6

The ISA bus version is know as the:

AGE:AGE image

Two ribbon cables connect the Geometry engine to the:

MRV:MRV image

This is the MicroChannel Raster Video Engine. It is based upon the RE 2.1 raster engine chip from SGI. The raster engine provides all the per-fragment and -pixel operations. It also contains the raster scanning hardware and video signal generation circuitry. It only obtains power and ground from the bus, no other bus signals are used. In addition to the two ribbon cables from the Geometry Engine, a third connection services the Genlock features of the Raster Engine. On the card edge connector, are the VGA passthrough connector and the HiRes video output connector. The Raster Video card contains the basic 8-bitplanes of framebuffer memory as well as 2 bitplanes of overlay framebuffer and 2 bits of window ID bitplanes, for a total of 12 bits per pixel.

IBM FRU: 71F1151
ADF:     none

The careful observer will note that the above picture is actually the IBM RS-6000 version of the MRV card. This card features an RGB video output connector (large w/plug-style connectors) and a genlock input/output connector (15-pin DSUB). If you happen to find an IBM-style card set and need the RGB video cable, let me know.

The SGI/ISA version is different in that it has two 15-bin high-density D-Sub connectors, upper one is VGA video input (passthrough with stereo display signals) and the lower one is video output, VGA/XGA-compatible. Other than that, the two cards are functionally identical.

The ISA bus version is know as the:

ARV:ARV image

This card requires external video DAC and optional framebuffer memory which is supplied by one of:

MDE:MDE image

This card supplies the 8-bit video DAC and the hardware cursor support for the MRV. With this card in place, the system can support up to 256 colors at 1280x1024 resolution. In place of this base level card, you can use the:

IBM FRU: 71F1117
ADF:     none

MEV:MEV image

This card supplies the additional bitplanes of memory to bring the system to 24 bits per pixel of normal framebuffer in addition to 2 additional overlay/popup bitplanes and 2 additional window ID planes, for a total of 32-bits per pixel. A fully configured frame buffer has a total of 1280x1024*(32/8) or 5MB of video RAM (VRAM) implemented in 256Kx8 ICs.

You'll notice that the VRAM is laid out in a 5xN array of chips. Each chip supplies 256 horizontal pixels (1280/5 = 256). However, to achive greater performance, the raster engine chip is designed to write up to 5 pixels at a time, so the five VRAM chips are interleaved; the first supplies pixels 1, 6, 11, etc. the second 2, 7, 12, etc. and so on.

IBM FRU: 71F1114
ADF:     none

MZB:MZB image

This is the optional 24-bit hardware z-buffer card. The function of the z-buffer is to perform hidden surface removal via a depth test mechanism. In the traditional application, each pixel's "Z" coordinate value is tested against the value already present in that location in the z-buffer. If it is smaller (i.e. closer to the eye) the pixel is updated with the current value and the z-buffer is updated. By controlling the z-buffer operation, a number of other useful operations can performed. For non-3D applications, the z-buffer can be used as an off-screen memory buffer for saving the contents of the normal framebuffer. As no host to adapter memory transfer takes place, this operation is very fast. The z-buffer is implemented in dynamic RAM (DRAM) and consists of 3.75 MB of DRAM.

IBM FRU: 42F6889
ADF:     none


You'll notice the ISA and MCA bus card sets share the 8 and 24 bit frame buffer and z-buffer daughter cards. In some MCA machins, such as the PS/2 Model 70, the MEV card will not fit. In the PS/2 Model 80, the MEV card will fit as it does in most ISA bus systems. The ISA bus cards will also operate in EISA bus systems.

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Last updated: 29.JAN.1999