Asymmetric vs Symmetric Multiprocessing

Asymmetric multiprocessing
Symmetric multiprocessing

Asymmetric multiprocessing

   In asymmetric multiprocessing the program tasks (or threads) are strictly divided by type between processors and typically, each processor has its own memory address space. These features make asymmetric multiprocessing difficult to implement. The two figures below are two examples of asymmetric multiprocessor configurations.

The PS/2 Server 195 and Server 295 were examples of servers using asymmetric multiprocessing.

Asymmetric Multiprocessing Example 1

This configuration has multiple memory units with some of those not shared by all processors.

Asymmetric Multiprocessing Example 2

This configuration has one processor doing all I/O.

Symmetric multiprocessing

   Symmetric multiprocessing (SMP) is the most common configuration of multiple processors. A typical SMP configuration has the following items:

  • It has multiple processors and exactly one of everything else: memory, I/O subsystem, operating system, etc.
  • The processors are symmetric, that is, they can do anything the others can. Each can look at or alter any element of memory, and each can do any kind of I/O.

It is symmetrical because the view from any processor of the rest of the system is exactly the same. The display below shows a typical implementation of SMP.

A Typical SMP Configuration

SMP is easier to implement in operating systems and is the method used most often in operating systems that support multiple processors. Operating systems that support SMP include:

  • OS/2 Warp Server 4.0
  • OS/2 for SMP 2.11
  • Windows NT 4.0
  • Novell NetWare 4.1 SMP
  • Novell UnixWare SMP 2.0
  • SCO Open Server 5.0 with SCO MPX 3.0
  • Banyan Vines

   If one processor fails, the others may still function. A reboot will still be required due to the fact that the design of an SMP configuration has every other component shared, including memory. If a processor fails, then it will invariably leave the memory in an unpredictable state, which could cause more problems for the remaining CPUs. Depending on the implementation of SMP on a server, the failed processor may or may not have to be physically removed before the system can restart.
   A very important consideration of SMP systems is the bandwidth of the other system components. Consider an analogy of a dog with two heads (a savage multi-headed pooch, as it were).

   It has the ability to eat (process) twice as much food (data) as a normal single-headed dog. However, to maximize the advantage of having two heads, it needs to have a throat (bus), stomach (disk) and digestive system (network) large enough to handle the output of the two heads. The alternative is for the heads to not eat as fast or to wait (wait state) for there to be sufficient swallowing capacity (bandwidth). If more heads were to be added, then the dog could eat a lot faster, but if the rest of the dog couldn't handle the throughput, then the heads would have to wait even more and the benefits of the extra heads would not be realized (and if the dog's owner can't feed it fast enough, he may get his hand bitten off).

   The point is that for SMP machines to be effective, the other subsystems have to have sufficient bandwidth to keep up with the multiple processors. For example, the IBM PC Server 720 implements a memory bus that has a bandwidth of 400 MBps. The IBM Streamer family of LAN adapters can process data from the network at the speed of the media without placing an extra burden on the CPUs. An IBM RAID subsystem utilizing data striping can provide very high bandwidth in SMP environments. These factors are very important when evaluating SMP systems.

The IBM PC Server 320, 325, 330, 520, 704 and 720 support SMP.

The Server 320 and 520 offer two-way SMP using a shared cache design. This design has one cache memory, which is accessed by the two processors.

The Server 720 uses a design where each processor has its own 512 KB (166 MHz models) or 2 MB (200 MHz models) cache.

The Server 325, 330 and 704 also use an independent cache design. However, the cache is integrated into the Pentium Pro processor. Refer to Cache for further information about the SMP designs of IBM servers and discussions of these alternatives in cache design.

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Louis F. Ohland, Peter H. Wendt, David L. Beem, William R. Walsh, Tatsuo Sunagawa, Tomáš Slavotínek, Jim Shorney, Tim N. Clarke, Kevin Bowling, and many others.

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