i960CA and i960CF Block Diagrams

Images on this page are from the Intel datasheets. Intel darned well retains the copyright to them.

i960 Family Overview

The 80960CF processor is the second in the series of 32-bit, RISC-style, superscalar i960(R) microprocessors that also includes the 80960CA and 80960HA/HD/HT. Socket- and object code-compatible with the 80960CA processor, the 80960CF features an expanded 4 Kbyte instruction cache and adds a 1 Kbyte data cache to significantly improve performance.

i960® CA/CF Superscalar 32-Bit Microprocessors HERE

Superscalar RISC core
1 KB two-way set associative instruction cache (i960 CA processor only)
4 KB two-way set associative instruction cache (i960 CF processor only)
1 Kbyte on-chip data RAM
4 DMA channels and a flexible interrupt controller integrated on-chipDirect Memory Access
De-Multiplexed bus

i80960Cx Architectural Comparison HERE

1.1.1 The 80960Cx Processor Family
   The 80960Cx family of processors are superscalar implementations of the i960 microprocessor architecture, and feature demultiplexed, 32-bit address and data buses. The two members of this family, the CA and CF, can execute up to three instructions per clock cycle. Due to the high
degree of parallelism and on-chip caches, these processors are well suited for high performance applications such as networking and high-end imaging.
   The 80960CA includes a 1 Kbyte, two-way set associative instruction cache and 1 Kbyte of on-chip data RAM. Data RAM is located in the processor's address space from locations 0000.0000H to 0000.03FFH. The CF processor enhances the CA feature set by increasing the instruction cache size to 4 Kbytes, and adding a 1 Kbyte direct-mapped write-through data cache. As with the CA, the CF contains 1 Kbyte of on-chip data RAM located from 0000.0000H to 0000.03FFH.
   The upper 16 Mbytes of the address space (FF00.0000H through FFFF.FFFFH) are reserved for implementation-specific functions. In general, an application must not access this space unless specifically required by the implementation. In the case of the CA and CF processors, the application must locate the Initialization Boot Record (IBR) at address FFFF.FF00H. Integrated peripherals include the Interrupt Controller and Direct Memory Access (DMA) Controller. The DMA peripheral is not available on the 80960Jx and 80960Hx processors.

80960CA-33, -25, -16, 32-Bit Embedded Processor
80960CF-40, -33, -25, -16 32-Bit Superscalar Embedded Microprocessor

The god Emperor of Microchannel
   I swapped in a i960CF into a Cheetah, dropped it into a 9590, hooked up a Quantum XP32150W, configured it and successfully ran diags on it.
   RAID 0 sure livens things up.

Casolai chimes in with:
  My new i960CF-40 CPU arrived today, and it works perfectly in the Passplay! Best of all, the benchmarks have speeded up.
Max cache speed was 17MB/s, now they are 19MB/s.
Max sequential read speed was 6MB/s, and now 7MB/s.

i960CA Processor - Block Diagram

80960CF Processor - Block Diagram

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