197-267 RS/6000 7012 Workstation/Server Model 397
197-273 RS/6000 7030 Wrkn Upgrade Model 397 Features Powerful POWER2 SuperChip

ENUS197-267 RS/6000 7012 Workstation/Server Model 397
ENUS197-273 RS/6000 7030 Wrkn Upgrade Model 397 Features Powerful P2SC

SA38-0545-00 7012 Models 300 Series Installation and Service Guide (PDF)
SA38-0544-00 7012 Models 300 Series Operator Guide (PDF) 

Thoughts of the POWER2 and POWER2 Super Chip (P2SC)

7012-397 Planar
7012-397 Power

LCD Monitor Success

Kevin Bowling reports:
   I can report success with a Dell 1800FP fed using a 7012-397 and GXT150M at 1280x1024.  I suspect most LCDs will work fine, but I'd buy from a return friendly store to be sure if you go the LCD route. 

The 397 has a 160MHz P2SC processor. This 32-bit RISC chip has 32KB of L1 instructional cache and either 64KB or 128KB of data cache, depending on the number of memory cards installed (two or four). 

Power2 Super Chip Technology
The Power2 Super Chip (P2SC) technology implemented in this machine is a next generation single
chip RISC processor with a 15 million transistor implementation of the POWER2 architecture. 

Instruction Cache Unit (ICU) includes a 32 KB, 128 byte line size, two-way set associative
cache. It fetches up to eight instructions from the cache per cycle and dispatches up to six
instructions per cycle. The FXU (Fixed Point Unit) includes two full function (arithmetic/
logic/load/store) units and eight instruction buffers. The FPU (Floating Point Unit) consists of two
floating point units which comply with and also features eight instruction buffers. 

Data Cache Unit  (DCU) supports a four way, set associative, store- back cache that operates
in either four word or eight word mode. In four word mode (two memory cards) a 64 KB data
cache with 128 Byte line size, and 2-128 byte store-back buffers is available. In eight word mode
(four memory cards) a 128 KB data cache with 256-byte line size, and 2-256 store-back buffers is available. 

Storage Control Unit  (SCU) which provides the memory interface and controls for the
processor complex, operates in either four or eight word mode and in either case the
processor-speed to memory-bus speed ratio is 2:1. Memory bus data integrity is provided by ECC
(error correction code) circuitry that corrects single bit errors and detects double bit errors.
Additional memory reliability functions such as bit steering (hot standby bit replaces single failed
memory bit), and bit scrubbing (prevents single bit errors from becoming double bit errors) are

Memory can be expanded to 1GB, memory bandwidth of 2.56GB per second.
Memory S6 Memory Card Memory cards must be installed in pairs.
The S.6 memory card illustration is HERE.
Base Memory Card, FRU 93H5994

Card MB  SIMM FRU (8 SIMM per card)
 32MB    39H8924 1Mx40,  4MB, 60 ns, E
 64MB    39H8925 2Mx40,  8MB, 60 ns, E
128MB    43G1796 4Mx40, 16MB, 60 ns, E
256MB    39H8312 8Mx40, 32MB, 60 ns, E

Two memory cards constitute a four-word memory system and support the 64KB data cache. Four memory cards installed make up an eight-word memory system and support the 128KB data cache.

The 397 has an 80MB/s MCA  bus that supports the high-speed data streaming protocol.

Content created and/or collected by:
Louis F. Ohland, Peter H. Wendt, David L. Beem, William R. Walsh, Tatsuo Sunagawa, Tomáš Slavotínek, Jim Shorney, Tim N. Clarke, Kevin Bowling, and many others.

Ardent Tool of Capitalism is maintained by Tomáš Slavotínek.
Last update: 08 May 2024 - Changelog | About | Legal & Contact