SSA 4-Port RAID Adapter 4-I


SSA 4-Port RAID Adapter Front
SSA 4-Port RAID Adapter Back
Optional SSA Fast-Write Cache Option Card

SSA 4-Port RAID Adapter Front FRU 96H9883 / FC 6217

D4 Status LED Loop B
D5 Status LED Loop A
J1,9 Slots for memory
J2,6 Internal SSA ports
J3 "B2" SSA Loop B Port 2
J4 Pads for 140-pin connector
J5 Socket for 4 MB Fast-Write Cache
J7 "B1" SSA Loop B Port 1
J8 "A2" SSA Loop A Port 2
J10 "A1" SSA Loop A Port 1
J14 PS/2 Serial Port (Unknown)
TH1 PTC Resistor
U1 96H9834
U2 50.0000 MHz osc
U3,5,8,10 TC559128AJ-20
U4 Xilinx XC4413-PQ240C 6070 (HardWire)
U6 31H8637 BIOS Odd?
U7 Phillips SCC2691AC1A28
U9 88G6298
U12 34G1521 "Miami" MCA iface
U13 Dallas DS1225AD-170 8Kx8 NVRAM
U14 40.000 MHz osc
U15 31H8636 BIOS Even?
U26-29 TC559128AJ-20 DRAM

FRU 96H9883 RSINFO says "96H9883 Not a valid FRU - Correct is FRU 89H5617 MCA 4-I adapter"

SIMMs in J1 & J9
   I have both slots filled with 4 MB SIMMs, 1Mx36 70 ns 5.0 V, P/N 82G6981. These have ten chips on one side of the PCB. There are 4 M514400C-70SJ (data) and one M512200-70SJ (parity) on each half.

Light Pipes on D4 & D5
   Both LEDs are normal LEDs on the PCB. There are light pipes to transmit the light to the outside.

Each pair of connectors has a green light that indicates the operational status of its related loop:

Status Meaning
Off Both SSA connectors are inactive. If disk drives or other SSA adapters are connected to these connectors, either those disk drives or adapters are failing, or their SSA links are not active.
Solid The light is on continuously when power is turned on to the adapter and both ports for that loop are operational; that is, the devices connected next to the adapter in the loop have power turned on to them, are connected correctly to the adapter, and are operational.
Slow Flash The light flashes continuously if one of the ports is not operational. That occurs when the cable to that port is not connected correctly or the device connected next to the adapter in the loop is not operational.

SSA 4-Port RAID Adapter Back

J12,13 Pads for 40-pin connector
U17 VLSI-ARM VY86C06040
U19,25 88H5516
U23,31 AM29F040-120EC

40 MHz version of the ARM6 Application-Specific Standard Product (ASSP) version of the new ARM processor, designed the VY86C06040, is pin-to-pin compatible with lower clock frequency versions.  It operates with a 40 MHz clock and exhibits a peak performance of 40 MIPS and a sustainable performance of 26 MIPS at 5.

Optional SSA Fast-Write Cache Option Card (#6222)

This is a 4MB fast-write optional feature that will plug into either SSA Multi-Initiator/RAID EL Adapter FC's 6215 or 6219.

When this feature is installed, data that is to be written to a disk drive is first written to a nonvolatile cache. This cache has a capacity of 4MB (plus ECC) and is on a removable daughter card. A battery on the daughter card enables it to retain data for up to 10 years. The daughter card can be moved to another Micro Channel SSA Multi-Initiator/RAID EL Adapter if the original adapter fails.

Using an SSA Fast-Write Cache Option Card enhances performance in two ways:

  • By reducing the adapter service time to less than 1 millisecond for write operations that use the cache (that is, for those operations that are not too long and for which there is space in the cache).
  • By joining split sequential write operations into larger data transfers when destaging to the disk drives.

Using an SSA Fast-Write Cache Option Card might reduce performance because:

  • Additional firmware overhead for moving data from the disk drive to the cache and back reduces the number of operations per second possible.
  • Longer internal bus cycles are needed when moving data from the disk drive to the cache; this reduces the available internal bandwidth.

Installing the Collar and Pin of the Fast-Write Cache Option Card

Content created and/or collected by:
Louis F. Ohland, Peter H. Wendt, David L. Beem, William R. Walsh, Tatsuo Sunagawa, Tomáš Slavotínek, Jim Shorney, Tim N. Clarke, Kevin Bowling, and many others.

Ardent Tool of Capitalism is maintained by Tomáš Slavotínek.
Last update: 08 May 2024 - Changelog | About | Legal & Contact