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MC146818A Advance Information (alt)
User Considerations for MC146818 RTC Applications (App. note AN894)
Package Types
Compatibility
Clearing Contents
Clock Operation
Package Types
| 24-Pin DIP [P] |
28-Pin PLCC [FN] |
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Vss is the more negative side of the supply voltage (Ground).
Vdd is the more positive side of the supply voltage (+5 V).
Compatibility
Motorola MC146818AP is a 24-pin DIP chip, usually installed in a socket.
Compatible chips are made by several manufacturers including Hitachi
(HD146818AP) and Samsung (KS82C6818A). The number on the chip should end in
6818.
Although this chip is pin-compatible with the Dallas 1287/1287A, there is no
built-in battery.
Clearing Contents
Since the MC146818AP doesn't have an internal battery, the CMOS RAM can be
cleared on this chip by just removing it from the socket for a few seconds and
replacing it.
To reduce chances of damage to the chip, it is preferable instead to short
pins 12 and 24 for a few seconds (with power off).
Clock Operation (from Franc Zabkar)
There are two clocks, a "hardware" clock and a "software" clock.
The hardware clock is maintained by an MC146818 compatible RTC which is
operated at a crystal frequency of 32.768 kHz. This crystal is usually packaged
in a small tubular metal can. The RTC continuously updates the date and time in
CMOS RAM. The smallest increment is 1 sec.
DOS and Windows maintain a separate software clock derived from the 14.31818
MHz crystal (usually a rectangular 4-pin oscillator in a metal package). This
clock is divided by 12 to produce a 1.19318 MHz clock which is then applied to
a timer IC. Channel 0 of this timer IC is programmed to generate an interrupt
(IRQ0) 18.2065 times per second (= 1.19318M / 64K). Hence, each tick of the
software clock corresponds to 54.9 msec. The S/W time is stored in RAM as the
total number of ticks since midnight. It is initialized from the h/w clock at
bootup.
Since the two crystals may drift from their nominal values, it is possible
that the S/W and H/W clocks may not correspond. The frequency of the 14.31818
MHz crystal may sometimes be trimmed for better accuracy by adjusting a small
variable capacitor located nearby.
Another reason for the S/W clock lagging behind the H/W clock may be that
IRQ0 is not being regularly serviced, despite it having the highest priority.
Other devices may be demanding too much of the CPU's attention, thus causing
some timer interrupts to be missed. Some people claim that buggy power
management may also cause this.
This little QBASIC program reads the time in hh:mm:ss format:
PRINT "The H/W time is ";
FOR I = 4 TO 0 STEP -2
OUT &H70,I
PRINT HEX$(INP(&H71));" ";
NEXT I
PRINT
PRINT "The S/W time is ";TIME$
I have verified that writing directly to the H/W clock in CMOS RAM does not
affect the S/W clock until the next reboot. However, the TIME command at the
DOS prompt adjusts both the the H/W and S/W clocks simultaneously.
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