Many factors contribute to the superiority of the Micro Channel Architecture
over the AT architecture (or bus) system. The primary reason there has not been
a perceived advantage to the Micro Channel so far, is that it was designed for
a multitasking environment, and most end-users have utilized it in a
single-tasking manner. The true worth of the Micro Channel is especially
evident when multiple tasks are running (and optionally, multiple processors).
This is where the AT bus bogs down. A number of the more significant advantages
(in no particular order) are discussed in the following sections.
- Although this document refers specifically to the IBM Personal Computer AT,
the information applies equally to most so-called "100% AT-Compatible" systems.
Details may differ from machine to machine, however, so be sure to contact the
system vendors for specifics regarding their hardware.
- This document was not written for engineers, but for those looking for a
layman's understanding of the benefits provided by the Micro Channel
Architecture. Hence many concepts were simplified (and perhaps oversimplified
to the point where they are not precisely accurate from an engineer's
standpoint, but still serve as an effective overview for non-engineers). For
detailed Micro Channel specifications, to the point of timing diagrams and
adapter design, refer to the IBM Personal System/2 Hardware Interface Technical
Reference manual. Ordering instructions may be found at the end of this
Note: This article borrows heavily from a
document called "Micro Channel Architecture: Balance in the Multi-Tasking
Environment", by Chet Heath, IBM Senior Engineer and chief architect of the
Micro Channel. (Any IBM Rep or SE can download the document from a VM file
called "MCROCHNL PACKAGE" on the PCTOOLS Disk, which is only accessible to IBM
Micro Channel PS/2s make extensive use of Large Scale Integration (LSI) and
Surface Mount Technology (SMT). LSI improves reliability by putting more
components and their connections within one chip. These interconnections are
far more reliable than solder connections, eliminating intermittent errors
caused by poor electrical connections. Using fewer components also means that
there are fewer components to fail.
The Micro Channel also simplifies adapter design by reducing the number of
signal lines connecting hardware. To support the same number of DMA devices as
the Micro Channel, a PC would require 16 additional signal lines. This means 31
contacts on every connector, module, or adapter, versus only 6 for a Micro
Channel machine. The miniaturized Micro Channel connectors also conserve system
board space (the 32-bit connectors are approximately the same length as the
16-bit AT connectors). Smaller circuitry means smaller motherboards and
adapters (or more circuitry on the same sized board), which results in smaller
Surface Mount Technology bonds all circuits directly to the surface of the
board, eliminating the need to drill holes through the board. This simplifies
robotic insertion of the components. The procedure of solder-bonding modules to
the circuit board avoids bent pins and thermal shocks to the joints (which lead
to unreliable, intermittent contacts).
Because of the heavy use of LSI and SMT, Micro Channel adapters require far
less power than conventional AT adapters (which use the less expensive
pin-in-hole technology). Lower power draw means that smaller, and less
expensive, power supplies may be used. This (plus the use of less power-hungry
3.5" hard disk drives) is the reason the 25MHz Model 70 has "only" a 132-watt
power supply, compared to AT-compatible systems containing 200+ watt power
supplies. Lower power also means less heat generated inside the computer (and
excess heat is the major cause of chip failure), as well as out. The Model 70
puts out approximately 750 BTUs, versus 1,000-1,500 BTUs for systems with
larger power supplies. This helps to reduce the expense of additional air
conditioning at sites with a large number of systems installed.
Also, although the Micro Channel adapters contain only 60% of the surface
area of AT adapters, the use of SMT allows both sides of the card to be used,
making it equivalent to 120% of the surface area of an AT card using
pin-in-hole mounting. Because of this, as well as the smaller components
themselves, SMT permits the placement of 8 times as many modules per adapter as
the older "pin-in-hole" technology.
Overall, field experience has shown that, on average, the PS/2 product line
is five times as reliable as the IBM PC family that preceded it.
A key feature that enhances the concurrent processing of OS/2 is the support
of bus masters. A bus master is a microprocessor which operates independently
of the system microprocessor, and may contain its own memory, hard disk drive
and/or slave coprocessors on a card, and run its own operating system. Bus
Masters allow the more efficient distribution of work throughout the system,
thus freeing the system microprocessor to perform more system management tasks,
while providing greater system capability. The Micro Channel can support up to
15 bus masters that can take control of the I/O bus to move blocks of data.
These bus masters do NOT have to be from the Intel family of microprocessors.
They may be any kind of microprocessor, from any vendor.
Bus masters add another dimension to the multitasking environment, called
multiprocessing. Multiprocessing occurs when bus masters (usually intelligent
I/O adapters) communicate directly with system memory or with other I/O
devices. Bus masters permit the system to transfer more data in less time than
is possible without bus masters, because multiple bus masters may be
transferring data concurrently.
Bus masters allow the creation of "intelligent subsystems", which use
microprocessors dedicated to a specific task in order to provide better
performance. For example, a board containing a 12MHz 286 chip and 2MB of memory
for disk caching might be added to a PS/2 to do nothing but disk drive data
transfer. Or a high-speed Intel or Texas Instruments graphics chip and 1MB of
memory for video processing might be used for CAD/CAM. Or a Motorola 68030 chip
and 6MB of RAM might be added for desktop publishing. Or the IBM PS/2 Wizard
adapter, with a 33MHz Intel i860 numeric processor, for heavy-duty
Similarly, LAN or communications subsystems can be designed (such as the IBM
ARTIC Portmaster adapter, for high-speed serial communications). In fact, all
of the above, and more, can be in the same system unit (assuming enough open
adapter slots) at the same time, and all will be running independently of the
system processor, and each other. AND each bus master could "talk" directly
with one another, totally bypassing the system bus which may be running at a
much slower rate than the bus masters. For example, the bus in a 20MHz Model
70-121 runs at 10MHz; however a 33MHz i860 bus master and a 25MHz 68030 bus
master could communicate directly at 25MHz (the lowest common denominator),
without tying up "traffic" on the system bus, or having to slow down to the bus
The only conflicts that might occur would be when two bus masters try to use
the same common resource (such as a diskette drive or other device not on the
bus master card). In this event, the Central Arbiter will determine which bus
master gets control (based on priority level); the others will wait their
If a multiprocessing operating system is used, each application could
execute on a different microprocessor, if desired. Additionally, one integrated
application would be able to use several different microprocessors for multiple
tasks. Thus it might use one 386 for sorting a file, while another 386 (with
its own 387) is used for recalculating a spreadsheet, and a graphics chip is
being used for graphing the result of the recalc, and a communications bus
master is downloading the next file to process. Then a 68020 might be used for
output to a laser printer.
The AT architecture does not easily lend itself to bus mastering, because it
was developed for the single-tasking environment. Thus there is no standardized
protocol defined for bus master arbitration in the AT bus, as there is in the
Micro Channel Architecture. This means there is potential for conflicts between
multiple bus masters in an AT bus system.
Even if intelligent subsystems were to be used with the AT architecture, the
system processor is still the only element capable of moving blocks of data to
and from multiple disk drives, or I/O devices, because the AT DMA controller
does not support burst mode. This results in an unavoidable bottleneck.
In the AT design, data flow consists of many stops and starts. First the
processor signals that it is going to send one byte of data, then it sends the
data, and finally indicates that it is ready to send another byte. This occurs
for each and every byte. These constant start/stops greatly impede the flow of
data. The processor becomes a point of congestion as it is the only element in
the system capable of moving continuous blocks of data. This is compounded in a
multitasking environment, where multiple programs are each trying to transmit
large blocks of data concurrently. By comparison, the Micro Channel allows a
device to move large blocks of data in bursts. Data bursts can be transferred
to and from the I/O device at up to 18.7 MegaBYTES per second (for a 32-bit I/O
device), by going through the DMA controller instead of the system
microprocessor (which is free to do other tasks).
When IBM released the original IBM Personal Computer, it included support
for three 8-bit non-bursting DMA channels. The IBM PC/AT increased the number
of non-bursting DMA channels to seven (three 16-bit, and four 8-bit). Of these,
only the original three 8-bit DMA channels are typically used by AT adapters,
(so that the adapters could also be used in the PC). With only three 8-bit DMA
channels available, no more than three adapters may use DMA (non-bursting)
transfers; and only one at a time.
The Micro Channel, by comparison, allows up to fifteen DMA devices to be
installed, up to eight of which can be transferring at the same time, at burst
mode transfer rates, through eight 32-bit DMA channels. This becomes especially
important in a multitasking environment, where system resources are at a
Higher Performance Data Transfers
The first new capability announced is the ability of Micro Channel systems
to transfer data at up to 160 Megabytes per second (MBps). The basic data
transfer rate of current systems is up to 20 MBps. In a basic data transfer
cycle, addresses and data alternate every 100 ns (for a total of 200 ns). A new
feature, called Streaming Data Mode, sends the address in the first 100 ns,
followed by only data in each successive 100 ns period. This allows a data
transfer rate of up to 40 MBps.
By using multiplexing techniques, on a 32-bit data bus, 64-bit data
transfers are possible. (64-bit data transfers between an adapter and the
system processor requires a 32-bit adapter.) Combining this with the Streaming
Data procedure yields data transfer rates of up to 80 MBps. In the future, with
faster microprocessors yielding shorter cycle times, data transfer rates of up
to 160 MBps will be possible.
Fault Detection and Isolation Features
In addition to memory parity checking (implemented in current systems), Data
Parity Checking and Address Parity Checking, as well as Synchronous Channel
Checking have been defined for future implementation.
Data Parity provides verification of data transferred across the Micro
Channel bus, as Address Parity provides for verification of address
information. In addition, Synchronous Channel Check allows error information to
be signaled in synch with the information being transferred. These capabilities
enable adapters and motherboards to be designed with much higher error
detection capabilities, and will allow better software recovery in the
Enhanced Programmability Features
Current Micro Channel implementation requires adapters to be designed with
unique adapter addresses built in, to avoid conflicts between adapters. This
requirement is eliminated for future systems. The architecture now allows the
assignment of I/O addresses by the setup program during installation.
The Subsystem Control Block Architecture defines a consistent software
protocol by which bus masters may communicate and exchange information. The SCB
architecture allows for transfer of command, data, and status information
between different bus masters, and between one bus master and the system
processor. This will make it easier to develop intelligent subsystems.
Relationship to Current and Future Systems
All of the Micro Channel capabilities described above (except for assignment
of I/O addresses) may be implemented in current systems via adapters. Future
systems can implement all of these capabilities on the motherboard, as well as
on adapters. In addition, these functions may be used between adapters, between
the system processor and adapters, as well as between system memory and
adapters. Because of this, the operating system doesn't have to worry about
matching the capabilities of the various components. Data transfers will occur
at the level of the HIGHEST common denominator (i.e.. using those capabilities
enabled at both ends).
Thus, even in a current system, which does not contain these new functions,
two "advanced" adapters would be able to initiate 64-bit data transfers between
themselves (although transfers between one of these adapters and the system
processor would still be 32-bit), for example.
Because the AT was designed for a single-tasking environment, it cannot
allocate and share system resources easily. Conflicts can be caused by two or
more adapters attempting to use the same DMA Channel, I/O Address, Memory
Address, Interrupt Level, ROM location, or memory-mapped I/O address. Therefore
many combinations of adapters are impossible to use concurrently in the AT bus,
such as Bisynchronous (Bisync) and Synchronous Data Link Control (SDLC)
adapters, and some network adapters when used in conjunction with Async,
Bisync, SDLC, or hard disk controllers. This is only a sample of the possible
conflicts. The more adapters you put in a system, the more possible
combinations of resources required, and the greater the likelihood of two or
more adapters conflicting.
System resource sharing is even more complex in a multitasking environment,
because two applications may require the use of the same type of system
resources at the same time. To redesign today's adapters with enough DIP
switches and/or jumpers to accommodate all possible combinations of memory,
I/O, etc., described above, would require up to 15 switches in a system with 8
adapters or less: 4 for interrupt assignments, 4 for DMA channel selection, 3
for I/O address selection, and 4 more for adapter ROM addresses. On top of
that, memory boards would require still more switches to specify starting
addresses and lengths for each block of memory.
This is why IBM developed Programmable Option Select (POS). POS identifies
the type of adapter in each slot, and automatically configures it, based on
information stored in an Adapter Description File (ADF) supplied with every
adapter. This unique function eliminates the need for the many DIP switches
often found on AT adapters. It also saves the time spent looking up the DIP
switch settings, and then actually changing them. The POS method is not only
faster than the manual means, but also more accurate: the ADF supplied by the
adapter vendor changes the settings; not the user.
Running multiple async communications programs concurrently requires the use
of multiple interrupts. An AT is limited to only two Async (serial) ports
concurrently, because only two interrupts (INT 4 for COM1, and INT 3 for
COM2...COMx) are allocated for async communication use; and the AT cannot share
interrupts. The Micro Channel, on the other hand, CAN share interrupts (due to
the Micro Channel Architecture's use of Level-Sensitive Interrupts, rather than
the Edge-Triggered Interrupts used by the PC bus).
This means that as many as EIGHT serial devices can use those two interrupts
in the current implementation of the Micro Channel (although the current
versions of OS/2 and DOS only support 3 or 4 serial ports, respectively, in a
Micro Channel system). In addition, the Micro Channel Architecture has the
potential for handling as many as 512 serial devices in the future.