Group 1 POS Registers

Group 1 POS Register 2 (Hex 0102)
Group 1 POS Register 3 (Hex 0103)
   Memory Connector
   Parity or ECC
   Operator Panel Information
Group 1 POS Register 4 (Hex 0104)
Group 1 POS Register 5 (Hex 0105)


Group 1 POS Register 2 (Hex 0102)

When group 1 is in setup mode, this read/write register controls the diskette drive controller and parallel port B.

+-----------------------------------------------+
|  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |
|-----+-----------+-----+-----+-----+-----+-----|
| BID |    SEL    | PP  |  1  |  0  | DDE | ENA |
+-----------------------------------------------+
 BID:    Disable bidirectional mode
 SELECT: Parallel port B select
 PP:     Enable parallel port B
 DDE:    Enable diskette drives
 ENA:    Enable system board functions
 R:      Reserved

BID The disable-bidirectional-mode fit controls whether parallel port B is configured as a bidirectional parallel port (extended mode) or unidirectional parallel port (sometimes called the compatible mode). When this bit is set to 1, the parallel port is an output-port only. When the bit is set to 0, the parallel port is bidirectional. The default is bidirectional mode.

SELECT The parallel-port-select bits configure parallel port B on the system board.

Parallel Port B Select Bits

Bits
6 5
AssignmentAddress
(hex)
Int.
Level
0 0Parallel 103BC-03BF*7
0 1Parallel 20378-037D7
1 0Parallel 30278-027D7
1 1Parallel 41378-137D7
* For DMA operations, the addresses are hex 1278-127D.

PP The enable-parallel-port bit enables and disables parallel port B on the system board. When this bit and bit 0 are set to 1, parallel port B is enabled. When either bit is set to 0, the parallel port is disabled.

DDE The enable-diskette-drives bit enables and disables the diskette drive controller. When this bit and bit 0 are set to 1, the controller is enabled. When either bit is set to 0, the controller is disabled.

ENA The enable-system-board-I/O bit provides a single bit to disable I/O controllers on the system board (diskette drive controller, both serial ports, and parallel port B). When this bit is set to 0, all system board functions are disabled. When this bit is set to 1, these functions can be controlled by their respective bits.

Note: Disabling the system board functions does not disable their interrupt request signals. Therefore, the interrupts must be disabled individually before the device is disabled.


Group 1 POS Register 3 (Hex 0103)

This register acts as a data port and is used to access information about memory connectors on the system board (see Memory Connectors). To access the information, write the desired index to address 0103h, then read 0103h.

Write

+-----------------------------------------------+
|  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |
|-----------------+-----------------+-----+-----|
|    Reserved     |      Index      |  R  |  1  |
+-----------------------------------------------+

Read

The following figure shows the possible index values and the information that is returned when the port is read.

+-----------------------------------------------+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |  INDEX VALUE  |
|---------------+---------------+---------------|
| Connector B1  |  Connector A1 |       0       |
|---------------+---------------+---------------|
| Connector B2  |  Connector A2 |       1       |
|---------------+---------------+---------------|
| Connector B3  |  Connector A3 |       2       |
|---------------+---------------+---------------|
| Connector B4  |  Connector A4 |       3       |
|-------------------------------+---------------|
| Parity/-ECC for all connectors|       4       |
|-------------------------------+---------------|
|  Operator panel information   |       7       |
+-----------------------------------------------+

Memory Connector Information

The memory in each connector is defined by four presence detect signals and a signal that indicates the type of error detection used (ECC or parity). The state of the presence-detect signals for each connector is reflected in a four-bit field. For coding of the presence-detection signals, see Memory-Presence Detect.

+-------------------------------+
|   3   |   2   |   1   |   0   |
|-------+-------+-------+-------|
|  PD3  |  PD2  |  PD1  |  PD0  |
+-------------------------------+

Parity/-ECC Information

The memory in each connector is also defined by an parity/-ECC signal. The state of this signal for all connectors is reflected in the byte returned for index 4. When a bit is 0, the corresponding connector contains ECC memory; when the bit is 1, the connector contains parity memory. The following figure shows the bit position for each connector.

+-----------------------------------------------+
|  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |
|-----+-----+-----+-----+-----+-----+-----+-----|
| B4  | A4  | B3  | A3  | B2  | A2  | B1  |  A1 |
+-----------------------------------------------+

Operator Panel Information

The following information is returned by reading POS Register 3 after the appropriate index value has been written to POS Register 3.

+-----------------------------------------------+
|  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |
|-----------------+-----+-----------------------|
|     Reserved    | UA  |         Panel         |
+-----------------------------------------------+
 UA:    Unattended power-on status
 PANEL: Operator panel present

UA The unattended-power-on-status bit indicates whether the power switch is in the standby mode or the power-on mode. When this bit is 0, the power switch is in the standby mode, and the system was powered-on through the wake-up or kickstart feature. If the bit is 1, the system was powered-on with the power switch.

PANEL The panel field is a 4-bit field that identifies the operator panel.


Group 1 POS Register 4 (Hex 0104)

This register is used to control the diskette drive arbitration.

+-----------------------------------------------+
|  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |
|-----------+-----+-----+-----------------------|
|  Reserved | BE  |  F  |          ARB          |
+-----------------------------------------------+
 BE:  Diskette burst enable
 F:   Diskette fairness enable
 ARB: Diskette arbitration level

BE The burst-enable bit determines whether the diskette-drive controller performs burst transfers to memory. Burst transfers reduce the time it takes to transfer data because the controller transfers a block of data each time it gets control of the system bus.

When this bit is set to 1, burst transfers are disabled. When this bit is set to 0, burst transfers are enabled.

F The fairness-enable bit determines whether the diskette drive controller uses fairness when arbitrating for control of the system channel. When this bit is set to 1, fairness is enabled for the diskette drive controller. When this bit is set to 0, fairness is disabled.

Note: Fairness is disabled during POST and should not be changed.

ARB The diskette-drive arbitration-level bits select the arbitration level used by the diskette drive controller. The default arbitration value is 2.


Group 1 POS Register 5 (Hex 0105)

This register is used to specify the arbitration level for parallel port B.

+-----------------------------------------------+
|  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |
|-----------------------+-----------------------|
|       Reserved        |        Arb Level      |
+-----------------------------------------------+

Arb Level The parallel-port arbitration-level bits select the arbitration level used by parallel port B.

Content created and/or collected by:
Louis Ohland, Peter Wendt, David Beem, William Walsh, Tatsuo Sunagawa, Jim Shorney, Tim Clarke, Kevin Bowling, Tomáš Slavotínek, and many others.

Ardent Tool of Capitalism - MAD Edition! is maintained by Tomáš Slavotínek.
Last update: 25 Nov 2022 - Changelog | Legal Info & Contact