Cirrus Logic CL-PX1070
Digital Video Processor

Block Diagram

Developed by Cirrus Logic's Pixel Semiconductor subsidiary; unveiled in 1994.
Sources archived HERE and HERE.


  • Pin-compatible with the CL-PX2070 (alt)
  • Complete frame buffer control
  • Integrated ISA, Micro Channel, and host bus interface
  • Supports up to three simultaneous video data streams
  • Supports both YUV and RGB formats
  • Video stream format conversion
  • Color space conversion
  • 0.5 - 8 MB of frame buffer memory
  • Programmable, triple-channel LUT RAM for gamma correction
  • Prescaling, zoom, and windowing
  • Interfaces to CODECs, decoders, and encoders
  • Graphic and bit-mapped stream support
  • Programmable sync slave or master
  • Convenient interface to the CL-PX4072 decoder

The CL-PX1070 digital video processor (DVP) provides a powerful, cost-effective bridge between computer graphics and video images. The CL-PX1070 is ideal for realtime digital video processing, video teleconferencing, video-playback acceleration, and video capture.

It's a low-cost version of the CL-PX2070. The main differences between the two chips are:

  • CL-PX1070 supports one video display window; CL-PX2070 supports four
  • CL-PX1070 supports three object buffers; CL-PX2070 supports eight

Block Diagram

[Functional Block Diagram]

The CL-PX1070 DVP incorporates Input Processor Units (IPU) in the chip's Video Processor Unit (VPU); as well as a Video Bus Unit (VBU) consisting of a Video Interface Unit (VIU) and Video Synchronization Unit (VSU); Bus Interface Unit (BIU); and Reference Frame Unit (RFU).

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Last update: 05 Dec 2023 - Changelog | Legal Info & Contact