SDL CP Codes

Early 4-digit checkpoint codes for T3/T4 complexes

Introduction
SDL CP Codes
SDL CP Sequence

Source: Peter H. Wendt's CSIPH post, Type 3 and Type 4 complex firmware.
Compiled by Tomáš Slavotínek.


Introduction

The 4-digit checkpoint codes listed here are outputted by early POST code through the Serial Diagnostic Link (SDL). This alternative path is used because the main complex interface and planar logic have not been tested yet and therefore shouldn't be relied upon to output diagnostic information.

The ROM-resident POST code of the Type 3 complex outputs these CP codes to the serial link port, however, the diagnostic header is not populated on the production level boards. Therefore the codes can't be observed or captured by normal means. (A special display board is required - one that was likely never released by IBM.)

In the case of the Type 4 complexes, the SDL cable must be installed and the SDL Diagnostics Jumper must be set appropriately for the codes to appear on the Op Panel display.


SDL CP Codes

CPDescriptionComplex
0110Check processor
0120ROM checksumT3, T4
0130Check power on values for memory controller registersT3, T4
0131Check power on values for BIU controller registersT3, T4
0140Check local registers on processor cardT3
0150Check JTAG device ID and static captureT3, T4
0151Verify complex interconnect (9595 2S2P planar only)T4
0160Check L2 cacheT3
0170Check L1 cacheT3
0180Check memory controller registersT3, T4
0181Test memory address bus on processor cardT3
0190Check power on values for DMA controller registersT3, T4
0191Check DMA controller registersT3, T4
0192Initialize DMA controller static captureT3, T4
0193Test DMA transfers
0210Check BIU controller registers captureT3, T4
0220Verify JTAG cycle capture on LEPBT3, T4
0230Verify error detection and enable detection for parity errorsT3
0240Verify ECC logic of the Memory Controller and Memory Data Bus BuffersT3
0250Verify DMA transferT3
0260L1 cache snoop test
0270L2 cache snoop test


SDL CP Sequence

The expected cold boot checkpoint sequence is as follows:

Type 3 (M; revision 0)

CP: 0120 -> 0140 -> 0130 -> 0131 -> 0190 -> 0160 -> 0170 -> 0150 -> 0180 -> 0191 -> 0210 -> 0220 -> 0192 -> * -> 0230 -> 0240 -> 0181

* - standard 2-digit CP codes are being outputted at this point (up to CP: 10)

Type 4 (N, P, Q, Y; revisions 02 - 10)

CP: 0120 -> 0130 -> 0131 -> 0190 -> 0150 -> 0180 -> 0191 -> 0210 -> 0220 -> [0192] -> 0151

Warm boot POST outputs only the codes shown in brackets.

Once this sequence is finished, the POST routine starts using the planar (parallel) Op Panel interface and begins the 2-digit CP code sequence.

Content created and/or collected by:
Louis Ohland, Peter Wendt, David Beem, William Walsh, Tatsuo Sunagawa, Jim Shorney, Tim Clarke, Kevin Bowling, Tomáš Slavotínek, and many others.

Ardent Tool of Capitalism - MAD Edition! is maintained by Tomáš Slavotínek.
Last update: 25 Nov 2022 - Changelog | Legal Info & Contact