CP "Checkpoint" Codes

Second Draft, 05. September 1999

This page contains the most common CP codes for the Premium Line PS/2 MCA-machines.

CP stands for Check Points and these CP codes represent a function the system is just proceeding during startup.

The POST Stage 1 is the Power On Self Test carried out after a Cold Start (Power On); the Post Stage 2 is carried out after the stage 1 POST and after a warm boot (with [CTRL]+[ALT]+[DEL]).

The IBM PS/2 Mod. 95 shows the CP-codes on its LED-panel in the system unit front - all other models show the CP-Codes in the bottom line of the screen. However: some are not shown logically, during the time the screen is blanked and the video subsystem is disabled.

On PS/2 Models the CP-codes are also sent to the LPT-port !

If you can handle a solder iron you could create a little adapter to enable you reading the CP codes - either with a separate hardware logic or another PS/2 machine.
For details see here !

CP output during Stage 1 POST
CPDescription
01Disable clock interrupts, turn off screen,
mask off parity, initialize interrupt controller,
initialize error logging formats
02Memory DMA refresh test
03Channel reset
04Test planar ports (94, 96, 100, 102)
initialize default planar POS
05Check CMOS/NVRAM for validity,
initialize EXPRESSWAY (on Model 90 systems only)
06Initialize dot clock
07Enable base memory
08Base memory testing - data integrity
09Base memory testing - addressability
0FFatal base memory error - recovery not successful
10Start up drive 80
11Enable extended memory, initialize base memory,
disable SRAM, reset parity/channel check.
Initialize row, column of cursor.
12Test protected mode
14Initialize the 8259 interrupt controller
15Initialize the interrupt vectors
16Initialize BIOS interrupt vectors
17Verify DMA transfers
18POS setup, set CMOS clock
1ASet divide-by-0 interrupt vector
24Set CMOS equipment byte
25Check for manufacturing boot request
30Test DMA transfers
34Protected mode Shutdown
35Test video card type error
40Check for video feature ROM and video presence
41Reset parity and channel checks, load NMI vector
with dummy interrupt handler, test timer,
load NMI vector to POST NMI handler
42Test interrupt mask register
43Test interrupt mask register with device interrupt
44Check hot interrupts
45Check hot interrupts without I/O-memory parity enabled
46Interrupt mask error
47Timer 2 read/write, verify Timer 0 bits
48Verify Timer 2 output
49Verify Timer 0 on off bits
4AVerify Timer 2 output
4BVerify Timer 0 interrupt
4CVerify Timer 0 count/refresh
4DVerify Timer 3 NMI
4ECheck keyboard controller for last command accepted
5CSet hardware interrupt vectors 0-7
5DSet hardware interrupt vectors 8-15
5ESet rest of interrupt vectors
5FTest serial port
62Turn on drive 0 motor Note 1)
64Test ASYNC registers, modem control lines,
and data loop.
If ASCII console selected - initialize
ASCII console as system display device
65Enable timer interrupts
66Check for manufacturing boot and unmask NMI interrupts Note 2)
6ECheck for system security or CE override conditions,
run diskette testing and setup, go load first IML image
80Start of IML process. SCSI POST
81Diskette IML. Load and verify IML boot record from diskette
82Disk IML. Load and verify IML boot record from disk
83Diskette IML. Diskette recovery from SCSI IML failure.
Load in and verify IML boot record from diskette
90 - B6Protected mode exception
BEBuild descriptor tables for protected mode Note 3)
BFCompletion of descriptor tables for protected mode
C0Base memory addressing test, extended memory enable,
base memory initialization
CACache testing (tag RAM, linefill, DMA snooping)
CBSecond Group Cache Testing - L1 DMA snoop
CCSecond Group Cache Testing - L1 linefill
CDSecond Group Cache Testing - non cacheable range boundary
CESecond Group Cache Testing - L2 DMA snoop
CFSecond Group Cache Testing - L2 linefill
EBDual Bus Interface Controller internal register error
F0Protected mode initialization
F1Test interrupts in protected mode
F2Test exception interrupt in protected mode
F3Verify 286 descriptor instructions in protected mode
F4Verify 286 BOUND instruction in protected mode
F5Verify PUSHALL/POPALL instructions in protected mode
F6Verify ACCESSRIGHTS function in protected mode
F7Verify ADJUSTRPL fields in protected mode
F8Verify LOAD instructions in protected mode
F9Verify LOAD instructions in protected mode (continued)
FATest low meg chip select in protected mode

Note 1)
This is the point where the SCSI-drives are started, when they are jumpered without the "Power On Startup" option jumper and use the "Start Device" command from the SCSI-Adapter instead.
Return to CP-code

Note 2)
At that point the cursor *should* jump to the top / right position on the screen on all IML-machines. However it does not on many older Mod. 90 and 95 and some Mod. 9556 / 9557. If you are fast enough you can start the reference from the IML-partition at that point with the keys [CTRL]+[ALT]+[INS]. The interval for this is pretty short though - only a few seconds.
Return to CP-code

Note 3)
After changes to the system memory the machine may hang around at that CP for a while - especially on memory expansions, but also after general changes to the system configuration.
Return to CP-code

CP output during Stage 2 POST
CPDescription
01Flush cache, enable first meg of memory as cacheable,
disable clock interrupts, mask off parity
04End Codes - OS loaded (static afterwards)
0BWrite output port command
0CTest Keyboard
0DWrite byte command to keyboard controller
0EKeyboard error
14Initialize the 8259 interrupt controller
15Initialize display row count
1BCount memory size
1CProtect mode entered, determine extended memory size
20Extended memory size determined, store in CMOS/NVRAM
21Extended memory size stored, enter real mode
22Return from count memory size
23Set real mode stack and data area
24Set CMOS equipment byte
34Protected mode shutdown
35Test video card type error
40Initialize the video subsystem, set ASCII vectors,
clear manufacturing error flags
41Reset the data segment
4FDetermine warm start
50Call extended memory testing
51Protect mode entered, retrieve extended memory size
52Address test extended memory
53Memory test extended memory
54Extended memory testing complete
55Check if password is enabled
56Keyboard and mouse testing
57Keyboard auxiliary device test
58Verify an interrupt is generated by the keyboard
59Keyboard stuck key error
5AAuxiliary device testing
5BReset timer, initialize keyboard
5FEnable Keyboard interrupts
60Enable diskette interrupt vector
61Diskette and FDC test
62Diskette and FDC test, diskette setup
63Initialize the BIOS Data Area
65Enable timer interrupts, check CMOS and battery,
check for memory configuration errors
66Initialize diskette setup
67Enable interrupts
68Initialize real mode data segment
69Perform ROM scan
6AInitialize printer parameters
6BSet CMOS RS232, calculate usable memory values for CMOS
6CInitialize Math Coprocessor
6DClose window, setup keyboard, initprogs,
set cache boundaries, enable cache, check full NVRAM
errorlog, set time of day, clear descriptor tables,
set POST stack, enable level 71-INT, return to overlay
6ECleanup tasks before leaving POST, run boot routine
6FBoot strap loader, Interrupt 19h
70Read primary disk/diskette boot record
71Reset disk/diskette
72Interrupt 18h path
73RPL via Interrupt 18h
74Load Operating System (not verified)
84 - 85Image overlay
86Store system partition pointer and system partition type.
Return from boot record
90 - B6Protected mode exception
BEBuild descriptor tables for protected mode
BFCompletion of descriptor tables for protected mode
D0BASIC and VPD copies from ROM to RAM
F0Protected mode initialization
F1Test interrupts in protected mode
F2Test exception interrupt in protected mode
F3Verify 286 descriptor instructions in protected mode
F4Verify 286 BOUND instruction in protected mode
F5Verify PUSHALL/POPALL instructions in protected mode
F6Verify ACCESSRIGHTS function in protected mode
F7Verify ADJUSTRPL fields in protected mode
F8Verify LOAD instructions in protected mode
F9Verify LOAD instructions in protected mode (continued)
FATest low meg chip select in protected mode


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