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Basic Data Transfers
Basic
Matched Memory
Matched Memory w/o Wait
Streaming Data Transfers
32-bit or 16-bit Streaming
64-bit Streaming
64-bit Streaming w/50 ns Cycle
Basic Data Transfer Cycle
The basic transfer cycle works by first defining the address (in memory or
I/O space) where a transfer is to occur, and then, in a second operation of
equal length actually transferring the data. Each half of the operation
(defining the address and data transfer) takes 100 ns, or 200 ns total.
This process is repeated until the entire block of data has been
transferred. Micro Channel - Basic Data Transfer (20 MBps) shows basic data
transfer in operation. Basic data transfer on the Micro Channel runs at 20 MBps
(each cycle takes 200 nanoseconds, and 32 bits or 4 bytes of data are
transferred at a time).
Five such "default" cycles can be performed in a millionth of a second. Each
cycle moves four or two bytes per transfer, yielding a data transfer rate of 20
MB/sec for 32-bit (4 byte) transfers or 10 MB/s for 16-bit (2 byte)
transfers.
Basic Data Transfer - 20 MB/sec for 32-bit transfers or 10 MB/s for 16-bit
transfers:
Matched Memory Cycle
MMC's basic transfer cycle works by first defining the address (in memory or
I/O space) where a transfer is to occur, inserting a wait state, and then
actually transferring the data. Each third of the operation (defining the
address, wait, and and data transfer) takes 62.5 ns, or 187.5 ns total.
Five and a third MM cycles can be completed in a millionth of a second. Each
cycle moves four or two bytes per transfer, yielding a data transfer rate of
21.33 MB/sec for 32-bit (4 byte) transfers or 10.66 MB/sec for 16-bit (2 byte)
transfers.
Matched Memory Cycle:
This transfer cycle is used when the memory on a Matched-Memory adapter is
not fast enough to operate in a system with zero wait states. Though this looks
really slow, it results in a transfer rate slightly above 20 MB/s.
Matched Memory cycle without Wait State
Total cycle time is 125 ns and for 32-bit transfers this results in a data
transfer rate of 32 MB/sec. Note: that the 16 MHz
8580 supports 62.5 ns address and data transfer cycles.
Matched Memory cycle without Wait State:
Streaming-Data Transfers
In Sep 1989, IBM announced three new procedures for higher data transfer
rates - 40 MB/s, 80 MB/s, and 160 MB/s. The 80 MB/sec streaming-data rate can
be obtained with existing hardware (as of 1991!). Streaming data is only
effective for applications that transfer large amounts of sequentially arranged
data.
However, in many cases, blocks transferred to and from memory are stored in
sequential addresses, so repeatedly sending the address for each 4 bytes is
unnecessary. With data streaming transfer the initial address is sent, then the
blocks of data are sent and it is then assumed that the data requests are
sequential. Micro Channel - Data Streaming Transfer (40 MBps) shows 40 MBps
data streaming in operation.
The actual data transfer rate achieved is a function of the total burst
(packet) length, where the overhead (arbitration process and the address
designation of the burst) is "amortized" over a large amount of data.
Applications that can benefit include high speed LAN adapters (FDDI), storage
devices (SCSI adapters, DASD), and channel-attached memory (memory cards).
Note: 80 and 160 MB/sec
streaming is only available on machines / adapters that have dual-path
bus capabilities. Both adapters / devices must support streaming.
32-bit or 16-bit Streaming
This is a refinement of the basic cycle. The data transfer is still preceded
by the address, but the address is designated at the beginning of the transfer
and incremented based on the number of bytes of information to be
transferred.
This reduces the cycle time to 100 ns and results in an instantaneous data
rate of 40 MB/sec for 32-bit transfers and 20 MB/sec for 16-bit transfers for
sequentially ordered data. Note: the Address bus has
nothing to do after the initial address. The 40 MB/sec rate is available on
single path systems.
32-bit or 16-bit Streaming - up to 40 MB/sec for 32-bit or 20 MB/s for
16-bit transfers:
64-bit Streaming
The address bus is used at the start of the data transfer for the address
but then is used to transfer data, resulting in a 64-bit data path. Transfer
rates of 80 MB/s can be achieved for sequentially ordered data. The 80 MB/s
data rate should be attainable with existing hardware. Note that a dual-path
system is required. The Type 3 and 4 complexes have the enhanced dual path
memory buses.
64-bit Streaming - up to 80 MB/sec:
64-bit Streaming with 50 ns cycle
The address bus is used at the start of the data transfer for the address
but then is used to transfer data, resulting in a 64-bit data path. The cycle
time has been reduced to 50 ns. There is only a 64-bit form of this
transfer.
It can support 160 MB/sec for sequentially ordered data. The 160 MB/sec may
require new signal drivers and recievers. (The Streaming-capable adapters may
have it already, like the Fast/Wide, FDDI, FW RAID...). A dual-path system is
required.
64-bit Streaming with 50 ns cycle - up to 160 MB/sec:
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