Basic Data Transfer Cycle
The basic transfer cycle works by first defining the address
(in memory or I/O space) where a transfer is to occur, and then, in a second
operation of equal length actually transferring the data. Each half of
the operation (defining the address and data transfer) takes 100ns, or
Basic Data Transfer - 20MB/sec for 32-bit transfers or 10MB/s for 16-bit transfers:
Matched Memory Cycle
MMC's basic transfer cycle works by first defining the
address (in memory or I/O space) where a transfer is to occur, inserting
a wait state, and then actually transferring the data. Each third of the
operation (defining the address, wait, and and data transfer) takes 62.5ns,
or 187.5ns total.
Matched Memory Cycle:
This transfer cycle is used when the memory on a Matched-Memory adapter is not fast enough to operate in a system with zero wait states. Though this looks really slow, it results in a transfer rate slightly above 20MB/s.
Matched Memory cycle without Wait State
Total cycle time is 125ns and for 32-bit transfers this results in a data transfer rate of 32MB/sec. Note that the 16MHz 8580 supports 62.5ns address and data transfer cycles.
Matched Memory cycle without Wait State:
In Sep 1989, IBM announced three new procedures for higher
data transfer rates- 40MB/s, 80MB/s, and 160MB/s. The 80MB/sec streaming-data
rate can be obtained with existing hardware (as of 1991!). Streaming data
is only effective for applications that transfer large amounts of sequentially
32-bit or 16-bit Streaming
This is a refinement of the basic cycle. The data transfer
is still preceeded by the address, but the address is designated at the
beginning of the transfer and incremented based on the number of bytes
of information to be transferred.
32-bit or 16-bit Streaming - up to 40MB/sec for 32-bit or 20MB/s for 16-bit transfers:
The address bus is used at the start of the data transfer for the address but then is used to transfer data, resulting in a 64-bit data path. Transfer rates of 80MB/s can be achieved for sequentially ordered data. The 80MB/s data rate should be attainable with existing hardware. Note that a dual-path system is required. The Type 3 and 4 complexes have the enhanced dual path memory buses.
64-bit Streaming - up to 80MB/sec:
64-bit Streaming with 50ns cycle
The address bus is used at the start of the data transfer
for the address but then is used to transfer data, resulting in a 64-bit
data path. The cycle time has been reduced to 50ns. There is only a 64-bit
form of this transfer.
64-bit Streaming with 50ns cycle - up to 160MB/sec: