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Introduction
SDL CP Codes
SDL CP Sequence
Source: Peter H. Wendt's CSIPH post, Type 3 and Type 4 complex firmware.
Compiled by Tomáš Slavotínek.
Introduction
The 4-digit checkpoint codes listed here are outputted by early POST code
through the Serial Diagnostic Link (SDL).
This alternative path is used because the main complex interface and planar
logic have not been tested yet and therefore shouldn't be relied upon to output
diagnostic information.
The ROM-resident POST code of the Type 3
complex outputs these CP codes to the serial link port, however, the
diagnostic header is not populated on the production level boards. Therefore
the codes can't be observed or captured by normal means. (A special display
board is required - one that was likely never released by IBM.)
In the case of the Type 4 complexes, the SDL
cable must be installed and the SDL
Diagnostics Jumper must be set appropriately for the codes to appear on the
Op Panel display.
SDL CP Codes
| CP | Description | Complex |
|---|
| 0110 | Check processor | — |
| 0120 | ROM checksum | T3, T4 |
| 0130 | Check power on values for memory controller registers | T3, T4 |
| 0131 | Check power on values for BIU controller registers | T3, T4 |
| 0140 | Check local registers on processor card | T3 |
| 0150 | Check JTAG device ID and static capture | T3, T4 |
| 0151 | Verify complex interconnect (9595 2S2P planar only) | T4 |
| 0160 | Check L2 cache | T3 |
| 0170 | Check L1 cache | T3 |
| 0180 | Check memory controller registers | T3, T4 |
| 0181 | Test memory address bus on processor card | T3 |
| 0190 | Check power on values for DMA controller registers | T3, T4 |
| 0191 | Check DMA controller registers | T3, T4 |
| 0192 | Initialize DMA controller static capture | T3, T4 |
| 0193 | Test DMA transfers | — |
| 0210 | Check BIU controller registers capture | T3, T4 |
| 0220 | Verify JTAG cycle capture on LEPB | T3, T4 |
| 0230 | Verify error detection and enable detection for parity errors | T3 |
| 0240 | Verify ECC logic of the Memory Controller and Memory Data Bus Buffers | T3 |
| 0250 | Verify DMA transfer | T3 |
| 0260 | L1 cache snoop test | — |
| 0270 | L2 cache snoop test | — |
LEPB = Low-End Parallel Bus aka Micro Channel.
SDL CP Sequence
The expected cold boot checkpoint sequence is as follows:
Type 3 (M; revision 0)
CP: 0120 -> 0140 -> 0130 -> 0131 -> 0190 -> 0160 -> 0170 -> 0150 -> 0180 -> 0191 -> 0210 -> 0220 -> 0192 -> * -> 0230 -> 0240 -> 0181
* - standard 2-digit CP codes are being outputted at this point (up to CP: 10)
Type 4 (N, P, Q, Y; revisions 02 - 10)
CP: 0120 -> 0130 -> 0131 -> 0190 -> 0150 -> 0180 -> 0191 -> 0210 -> 0220 -> [0192] -> 0151
Warm boot POST outputs only the codes shown in brackets.
Once this sequence is finished, the POST routine starts using the planar
(parallel) Op Panel interface and begins the 2-digit CP code sequence.
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