SGI IrisVision
Trademark Info

@8EE6.adf   SGI Micro-Channel IRISVISION Adapter 
"sabine" or "High Performance 3D Color Graphics Processor".devices.mca.8ee6

Roger Brown's Site (local copy)

The Very Unofficial IrisVison Home Page   By Roger Brown
IrisGL Application Programming Interface  (Same as below, but HTML) 
Graphics Library Programming Guide, Volume I 
Graphics Library Programming Guide, Volume II IrisVision Win 3.1 driver source - Thanks to Resman (Glory be unto him!)

IrisVision drivers and related software:

Note to PS/2 MicroChannel Users:
    * The Windows display driver (above) are for the ISA IRISVISION card, only. Unfortunately, it seems when Pellucid developed this driver, they did not include support for the MCA version of the board set. 

From the Lorenzo Mollicone Library:
IRISVISION Owner's Guide
ADI Driver User's Guide

From Roger Brown:

IrisVision Technical Reference. About 700 pages.
irisvision_technical_reference_toc.pdf   393,985
irisvision_technical_reference_1.pdf      30,153
irisvision_technical_reference_2.pdf     130,719
irisvision_technical_reference_3.pdf     894,054
irisvision_technical_reference_4.pdf    2,819,748
irisvision_technical_reference_5.pdf    7,749,509
irisvision_technical_reference_6.pdf   12,319,323
irisvision_technical_reference_7.pdf    7,216,138

IrisVision Cards
MEV2 Card
   ISA vs MCA MEV2
MZB1 Card
MGE2 Base Card To a separate page
MRV2 Card
IrisVision Block Diagram
Product Description
Timing Parameters
ADF Sections 

IRISVision General Components

MGE2 Geometry Engine (Card has both GE and HI)
The Host Interface subsystem interfaces to the host processor via the Micro Channel Architecture (MCA) bus. It provides all of the necessary data and control signals required by the MCA bus. It also interfaces to the other three subsystems over a local bus which is compatible with the SGI private bus. The Host Interface Subsystem provides the programmable Option Select (POS) registers which are used to configure the MCA bus interface aspects of the adapter.

MGE2 Geometry Engine (Card has both GE and HI)
The Geometry subsystem contains the Geometry Engine which is used to perform the geometric transformations and lighting calculations on the graphics data. It also performs the clipping and high level rendering calculations before sending the data to the Raster subsystem. The Geometry Engine performs high speed floating point calculations under the control of the onboard microcode.

The host system issues commands to the Geometry Engine by sending command tokens and data parameters down a FIFO. The Geometry Engine reads the FIFO and performs the desired functions. The Geometry Subsystem also contains hardware which controls the addressing of the hardware components in the Raster and Display Subsystems.

MRV2 Raster Video (both Raster and Display Subsystems)
The Raster subsystem receives instructions and other data parameters from the Geometry
Subsystem and does the low level rendering of the data into the image frame buffer bitplanes. It also handles the 2 buffer depth comparisons and updates if the optional Z buffer card is installed. The pixel values for each of the 1.3 million pixels on the 1280 by 1024 high resolution monitor are stored in the video random access memory (VRAM) frame buffer for display on the monitor at a selected refresh rate.

The Raster Subsystem provides the necessary data and control signals to manage the frame buffer bitplanes as well as the Window ID bitplanes and the Auxiliary bitplanes. The Window ID bitplanes are used to control the display format for up to sixteen different on screen windows. The Auxiliary bitplanes are used for drawing pop-up menus, overlays and underlays. The Raster Subsystem also contains two hardware cursor chips.

MRV2 Raster Video (both Raster and Display Subsystems)
   The Display Subsystem performs the necessary operations to convert the frame buffer image data into analog RGB signals which are sent to the high resolution RGB monitor. The Display Subsystem uses the Window ID bitplane data to determine the format of the pixel data stored in the frame buffer. The frame buffer pixel data can be either a color index value or an RGB value. The frame buffer bitplanes can also be subdivided into two buffers for flicker free motion of on screen objects.

  The Display Subsystem performs the necessary operations to access the frame buffer as a single buffer or as a double buffer. The Digital-to-Analog Converters (DACs) are used to convert the digital RGB data into analog RGB data which output to the monitor. The Display Subsystem also provides the necessary timing signals to allow four different types of monitors to be connected to the adapter.

MEV2 24 Bit Video Option FRU: 71F1114
P4 RGB Video 
P5 Video Bus 
P6 Utility Bus 
P7 Pixel Bus 
U1 MEV 1112  (VPD)
U15-39 Toshiba TC524258AJ-10
IDT 7164 
U61-63 Brooktree Bt457KPJ125 
U41,45,49,53,57 SGI XMAP2 L1A5081

Bt457KPJ125 125 MHz Monolithic CMOS 256 Color Palette RAMDAC Datasheet 

   This card supplies additional bitplanes of memory to bring the system to 24 bits per pixel of normal framebuffer in addition to 2 additional overlay/popup bitplanes and 2 additional window ID planes, for a total of 32-bits per pixel. A fully configured frame buffer has a total of  1280x1024*(32/8) or 5MB of video RAM (VRAM) implemented in 256Kx8 ICs.
   You'll notice that the VRAM is laid out in a 5xN array of chips. Each chip supplies 256 horizontal pixels (1280/5 = 256). However, to achieve greater performance, the raster engine chip is designed to write up to 5 pixels at a time, so the five VRAM chips are interleaved; the first supplies pixels 1, 6, 11, etc. the second 2, 7, 12, etc. and so on.

The MEV2 card is a daughter board which attaches to the MRV2 card. It has a VPD PROM and provides an additional 20 bitplanes of VRAM which are part of the Raster subsystem.
It also contains the five XMAPP2 chips, the 8K color map chip and the three DAC chips which are part of the Display subsystem and are described in the chapter on the Display subsystem. The card has the Utility bus, Video bus, Pixel bus and RGB connections described above for the MRV2 card.




Of course, the internal traces may be different, but the PCB layouts sure look the same, except the ISA version lacks U1 [not needed for ISA].

MZB1 24 Bit Video Buffer FRU: 42F6889
P8 Z Buffer Utility Bus 
U16-45 TMS44C256DJ-10 
     or TC514256AJ-10
U60 MZB 7923 (VPD)

   This is the optional 24-bit hardware z-buffer card. The function of the z-buffer is to perform hidden surface removal via a depth test mechanism. In the traditional application, each pixel's "Z" coordinate value is tested against the value already present in that location in the z-buffer. If it is smaller (i.e. closer to the eye) the pixel is updated with the current value and the z-buffer is updated. By controlling the z-buffer operation, a number of other useful operations can performed.

   For non-3D applications, the z-buffer can be used as an off-screen memory buffer for saving the contents of the normal framebuffer. As no host to adapter memory transfer takes place, this operation is very fast. The z-buffer is implemented in dynamic RAM (DRAM) and consists of 3.75 MB of DRAM.

MRV2 Raster Video FRU: 71F1151

J1 W3 video port
P2 Geometry Engine Bus
P3 Utility Bus
P4 RGB Video
P5 Video Bus
P6 Utility Bus 
P7 Pixel Bus
P8 Z Buffer Utility Bus 
U1 M1244 - 30MHz osc
U2 M1244 - 24.545452 MHz osc
U10 L1A4996 RE 2.1 C 
U28-32 TC524258AJ-10
U33-37 TC524258AJ-10
U38 Bt431KJP
U39 Bt431KJP
U47 Bt438KJP
U42 XC2018-70
U43 27C256
U46 111.518MHz osc
U60 MRV 1149 (VPD)

Bt431KJP Monolithic CMOS 64x64 Pixel Cursor Generator Datasheet 
Bt438KJP -
250 MHz Clock Generator Chip for CMOS RAMDACs  Datasheet 

30MHz osc - 15MHz for PAL and SECAM
24.54542MHz osc - 12.27MHz for RS170 30 Hz (NTSC)
111.518MHz osc - 1280x1024 at 60 Hz (NI) and 30 Hz (Int)

MC10H115P Quad Line Receiver
MC10H135P Dual J-K Master-Slave Flip-Flop
MC10H121P 4-Wide OR-AND/OR-AND Gate

   This is the MicroChannel Raster Video Engine. It is based upon the RE 2.1 raster engine chip from SGI. The raster engine provides all the per-fragment and -pixel operations. It also contains the raster scanning hardware and video signal generation circuitry. It only obtains power and ground from the bus, no other bus signals are used. In addition to the two ribbon cables from the Geometry Engine, a third connection services the Genlock features of the Raster Engine.

The Display State Machine (DSM) is built out of a XILINX 2018 programmable logic array, an 8K by 8-bit RAM, a Bt438 clock generator chip and other miscellaneous clock control circuitry. The 8K PROM contains the Xilinx logic configuration data and the four different monitor timing tables. On system reset the logic configuration is loaded into the Xilinx chip and the monitor timing tables are copied to the 2K RAM for faster access. The operation of the DSM is controlled by various bits in the display registers.

I cannot prove any of this... Right below U60 is two PLDs, a 16V8 and a 20V8.

Other than you can burn these to make anything you want, I've got nothing.

   On the card edge connector, are the VGA passthrough connector and the HiRes video output connector. The Raster Video card contains the basic 8-bitplanes of framebuffer memory as well as 2 bitplanes of overlay framebuffer and 2 bits of window ID bitplanes, for a total of 12 bpp.
   This card features an RGB video output connector (large w/plug-style connectors) and a genlock input/output connector (15-pin DSUB).
   The MZB1 plugs onto the back (circuitboard side) of this card (use the short screws). The MEV2 plugs on to the front side (component side) of the card (use long screws).

Connector cable (wide) 53F3271 80 pin .025 pitch HPDB 
Connector cable (narrow)  53F3272 40 pin .025 pitch HPDB 

Removing Connector Cable
   Squeeze the metal clips on the ends of the connectors and pull connector off header. 

Plugging Connector Cables Back On
   Squeeze the metal clips so that the loose ends of the clip enter the catch on the header. 

  The following block diagram is derived from the IrisVision Block Diagram on The Very Unofficial IrisVison Home Page

IrisVision Board Functional Diagrams

Product Description: 

Stolen from Roger Brown's The Very Unofficial IrisVison Home Page

   The IrisVision  hardware is nearly identical to the graphics sub-system in the SGI Personal Iris workstation introduced in 1988. The hardware supports a 5th generation geometry processing pipeline, the GE5, an 8 or 24 bit per pixel frame buffer, and a 24-bit per pixel z-buffer for hidden surface removal. The card set implements in hardware, the entire IrisGL graphics Application Programming Interface (API). 

Notable differences from the Personal Iris graphics are: 
     Uses 256K VRAM instead of 64K VRAM for reduced size 
     Has a 3 color cursor instead of 1 color for increased visibility 
     Has VGA pass-through capability for PC compatibility 

The card has a rich set of video and rendering modes consistent with the Personal Iris. 

Origins of the IrisVision
   The product came to life originally as an OEM graphics board set based upon the VME bus in the Personal IRIS . Later, IBM approached SGI to develop a Micro Channel Architecture (MCA) version of the card for use in their newly introduced RS-6000 Unix workstation. IBM licensed the MCA card design as well as the IrisGL graphics library from SGI. 

   In the process of testing the product, it was discovered that an IBM PS/2 model 70 personal computer running OS/2 could be used to run diagnostics and test programs on the card much easier than using the RS-6000. So a minimal device driver was written for the card and soon IBM was shipping product.  (Ed. Roger Brown can't find the "minimal OS/2 drivers" and he works for SGI.) 

   At some point, the light went off in someone's head; "Why don't we sell this board set for use in PCs?". IrisVision was born. Initially, the MCA card was re-designed to offer some features critical for the PC market, including standard 15-pin VGA-style video output and a 15-pin VGA passthrough input connector. The IBM genlock connector was moved to the top of the card, and stereo display signals were also brought out to the VGA passthrough connector. The card occupied 1 32-bit MCA slot and an adjacent 16/32 bit slot. One or two daughter boards provided framebuffer and z-buffer memory. 

   Work then began on the design of an Industry Standard Architecture (ISA or AT-bus) version of the card. It would occupy 2 16-bit ISA slots and use the identical daughter cards as the MCA (and IBM) versions of the board set. 

   The IrisGL API is implemented in a C-language library developed with the Metaware High-C 32-bit C compiler and the PharLap 32-bit DOS-Extender. It was designed to run in a full screen DOS environment. At the time, M/S Windows did not offer a 32-bit programming environment, so the PharLap DOS-Extender technology was the most sophisticated solution available. It features full 32-bit virtual addressing (2 GB application space), virtual memory support, and seamless integration of real and protected mode programs. The MetaWare High-C compiler is ANSI compatible and is just the ticket for compiling Unix source code to run under DOS-Extender on the IrisVision card. 


Original HERE
Video Resolution
Pixel Clock (MHz)
Horizontal Freq (KHz)
Frame Rate (Hz)
Field Rate (Hz)
Visible Pixels
Line Period (uS)

Blanking (uS)

Front Porch (uS)

Sync Width (uS)

Back Porch (uS)

Visible Lines
Front Porch (mS)

Sync Width (mS)

Back Porch (mS)


ADF Sections AdapterId 8EE6h "SGI Micro-Channel IRISVISION Adapter"

Interrupt Level
   Determines the interrupt level used by IRISVISION Adapter.
    <" Level 2 " >, 3, 4, 5, 6, 9, 10, 11, 12

Memory Mapped I/O Address Range
   Determines the range of Memory Mapped I/O addresses used by the IRISVISION Adapter.  The addresses in this range cannot be used by any other installed device.
   <" 0C0000 to 0C7FFF " >, 0C8000 to 0CFFFF, 0D0000 to 0D7FFF, 0D8000 to 0DFFFF

Arbitration Level
   Determines the bus arbitration level used.
  <" Arb Level 1 ">, 0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14

  Silicon Graphics, SGI, OpenGL, Personal Iris, and IrisVision are registered trademarks of Silicon Graphics, Inc. 

  I usually don't mess with Trademarks, but that of SGI is very classy Trademark Info just was too damn good. Class act, SGI! I wish M$ and their bloodsucking shark team was only a tenth as smooth as you! Sorry, SGI, Netscape makes them durned TM's and Registered marks look like ASCII. 

   SGI does not endorse any of the information on this page. They retain all rights to their trademarks. Further, this information is furnished on an "As Is" basis. If you fry your monitor or card, that's your problem. 

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