Selected IBM ASICs & Gate Arrays

List of IBM ASICs & Gate Arrays (basic info only)

10G4672 I/O Controller
90X8134 DMA Controller
71G0438 "System Controller"
SynchroStream Controller

10G4672 I/O Controller

IBM P/N:10G4672
Plant Codes:53 52; 93 14 [?]
Code Name:"Galaxy"?
Prod. Years:1992 - 1994?

Used On: Planars - 9553, 9556/57, Bermuda, Lacuna, 85 "X", 85 "N", 95A, 5550-486, Power 50/70, Power 60/80, Turbo 50/70, Turbo 60/80, Olivetti M6-5x0

The 10G4672 I/O Controller can be found on many late PS/2 planars and also on some 3rd party system boards. It integrates the following functions:

  • Micro Channel interface for internal peripherals (incl. POS)
  • Interrupt controller
  • Timers
  • Keyboard and mouse controller
  • Real time clock (RTC) and CMOS logic control (external)
  • 2x Serial interface
  • 1x Parallel interface
  • 82077 floppy disk controller (FDC) support (external)
  • EEPROM controller (external)

Information Sources: Reverse-engineering, Olivetti M6-520/540/560 Service Guide

90X8134 DMA Controller

IBM P/N:90X8134(ESD)
Package:PGA-112 (metal can)
Plant Codes:53 52; 53; 93 98; 98 [?]
Prod. Years:1988 - 1992?
Clock Freq.:8 - 10 (12?) MHz

Used On: Planars - 50Z, 55SX, 65SX, 70 T1, 70 T2, 80 T3, 5540, 5550-386, 7568 SR; Complexes - T0-, T0+, T1

The Direct Memory Access (DMA) controller allows I/O devices to transfer data directly to and from memory. DMA is a fast and efficient way to transfer blocks of data between I/O ports and memory. DMA operates without involving the CPU in the transfer. This allows the CPU to continue with other processing during the transfer.

The 90X8134 DMA controller is implemented as a gate array with 6000+ circuits and has the following functions and features:

  • Direct Memory Access (DMA)
  • Central Arbitration Control Point (CACP) - I/O bus arbitration
  • Refresh controller logic *
  • 16 MB address capability (24-bit address)
  • 8 DMA channels, each capable of transferring data between memory and I/O devices
    2 channels are programmable to service any bus master adapter
  • Serial DMA operation (separate read and write cycle for each transfer operation)
  • Device support for byte (8-bit) or word (16-bit) transfers
  • Auto-initialization of transferring parameter on each channel
  • Sharing of the processor's system bus interface and control logic

* In some applications (Type 1 complex) the 90X8134 DMA controller only initiates the memory refresh cycle. The memory controller sees these signals and refreshes the planar memory. This means that although the DMA controller can only address 16 MB, the system hardware can support more than 16 MB of memory.

Possibly pin-compatible with DMA Controller P/N 63F7520.

Information Sources: Personal System/2 Models 95 XP 486, 90 XP 486, 55 LS and P75 486 Fundamentals - Release 1.0 (pages 60-62 physical)

71G0438 "System Controller"

IBM P/N:71G0438
Plant Codes:93 14 [?]
Prod. Years:1993 - 1994?

Used On: Planars - Lacuna, Power 50/70, Power 55, Power 56/57, Power 60/80

Real name unknown. "System Controller" is a generic term used for ICs with similar functionality. There is a document that calls it the "SynchroStream Controller" (possibly because the chip serves the same role as the SSC), but that's the only known instance to use that name for this chip.

It implements the following functions:

  • Memory controller
  • I/O (Micro Channel) controller (BIU)
  • DMA controller (24-bit, PIO)
  • ECC logic
  • Buffers?

The chip is not pin- nor register-compatible with the SynchroStream Controller.

Known Issues

9576/9577 and Streaming Adapters (yellow - bad, blue - ok)

SynchroStream Controller

IBM P/N:50G8192, 8190587, 50G6871
Plant Codes:93; 51 [?]
Code Name:"Mad River"?
Prod. Years:1993 - 1994?
Clock Freq.:40 MHz?

Used On: Planars - Turbo 60/80, Olivetti M6-5x0; Complexes - all T4

More information HERE.

Content created and/or collected by:
Louis F. Ohland, Peter H. Wendt, David L. Beem, William R. Walsh, Tatsuo Sunagawa, Tomáš Slavotínek, Jim Shorney, Tim N. Clarke, Kevin Bowling, and many others.

Ardent Tool of Capitalism is maintained by Tomáš Slavotínek.
Last update: 08 May 2024 - Changelog | About | Legal & Contact